Vertical MRAM Cell Layout With Buried Bit Lines and GAA Switches
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Solution Overview
Problem
Existing vertical devices, particularly those with single-crystalline channel materials, face challenges in controlling gate length and high channel resistance when using polycrystalline materials, making it difficult to stack multiple devices and integrate buried bit lines.
Innovation Solution
A Magnetic Random Access Memory (MRAM) is developed using vertical switch devices with a single-crystalline semiconductor material in the active region, along with buried bit lines and self-aligned word lines, to improve device performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-crystalline channel material is used in vertical devices, then carrier mobility is improved and leakage current is reduced, but gate length control becomes difficult
Solution Approach 1:
The patent transitions from planar gate configuration to a vertical gate-all-around configuration, where the gate wraps around the channel in three dimensions. This dimensional change enables precise gate length control through vertical stacking while maintaining single-crystalline channel material for high carrier mobility and low leakage current.
Solution Approach 2:
The gate structure is nested around the channel in a gate-all-around configuration, with the gate wrapping completely around the channel region. This nested structure provides superior gate control compared to planar gates, enabling precise gate length definition while accommodating single-crystalline channel materials.
2Manufacturing precision
If a polycrystalline channel material is used, then gate length control is improved, but channel resistance increases greatly
Solution Approach 1:
The vertical gate-all-around configuration allows the use of single-crystalline channel materials by providing three-dimensional gate control. This dimensional transition eliminates the need to compromise channel material quality for gate length control, thereby maintaining low channel resistance while achieving precise dimensional definition.
3Productivity
If multiple vertical devices are stacked, then device integration is improved, but total resistance becomes excessively high
Solution Approach 1:
The patent employs selective doping in the source and drain regions adjacent to the channel, creating localized high-conductivity paths. This local quality enhancement reduces contact resistance at critical interfaces, enabling vertical device stacking with acceptable total resistance while maintaining high carrier mobility in the single-crystalline channel.
4Area of stationary object
If buried bit lines are formed below vertical transistors, then area is saved and manufacturing cost is reduced, but it becomes difficult to build buried bit lines with single-crystalline channel layers
Solution Approach 1:
The vertical gate-all-around configuration elevates the channel structure into the third dimension, creating vertical space above the substrate. This dimensional transition allows buried bit lines to be formed on the substrate level while the single-crystalline vertical transistor channels extend upward, eliminating the conflict between buried bit line formation and single-crystalline channel integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MRAM achieves improved device performance with high carrier mobility and low leakage current, while the buried bit lines facilitate area-saving integration and reduced manufacturing costs.
Implementation Method 1
a magnetic tunnel junction disposed on the switch device and electrically connected to a first terminal of the switch device
Data Source
AI summary
A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.