3-Terminal Vertical Multilayer Ceramic Capacitor ESL Reduction
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Solution Overview
Problem
Multilayer ceramic capacitors face performance deterioration due to increased equivalent series inductance (ESL) with miniaturization and high capacitance demands, affecting reliability and mounting defects, especially in integrated circuits where low inductance chip capacitors are required.
Innovation Solution
A 3-terminal vertical multilayer ceramic capacitor design with external electrodes spaced 500.7 μm or less and widths of 20.2 μm or more for improved adhesion and reduced ESL, featuring a ceramic body with dielectric layers and internal electrodes to minimize current loop length and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the capacitor size is reduced to meet miniaturization demands, then the capacitance density increases, but the equivalent series inductance (ESL) increases causing performance deterioration
Solution Approach 1:
The patent transitions from a conventional planar electrode layout to a vertical three-dimensional structure. The external electrodes are positioned at different heights on the ceramic body, creating a vertical current path that reduces the horizontal current loop area. This dimensional change allows miniaturization while maintaining low ESL characteristics by exploiting the third dimension (height) rather than expanding in the horizontal plane.
Solution Approach 2:
The patent optimizes specific geometric parameters of the external electrodes, including their positions, sizes, and spacing intervals. By carefully controlling these parameters, the design achieves a balance between reduced capacitor footprint and minimized ESL. The parameter optimization ensures that even in a compact form factor, the electrical performance requirements are met.
2Reliability
If the external electrodes are positioned closer to reduce current loop length, then the inductance decreases, but the adhesion strength and reliability are affected
Solution Approach 1:
The patent applies different design considerations to different regions of the external electrodes. The portions of external electrodes closer to each other (affecting inductance) are optimized for minimal spacing, while the portions extending along the ceramic body (affecting adhesion) are designed with sufficient length and proper termination. This localized optimization allows simultaneous achievement of low inductance and high adhesion strength.
3Reliability
If the external electrode widths are reduced to increase spacing, then the mounting defect rate decreases, but the adhesion strength is reduced
Solution Approach 1:
The patent compensates for reduced electrode width by utilizing the vertical dimension. The external electrodes extend along the height of the ceramic body, providing sufficient adhesion area despite narrower widths. This vertical extension maintains bonding strength while allowing closer horizontal spacing between electrodes, thereby reducing mounting defects.
Data Source
AI summary
There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more.