Vertical NAND Flash Memory Bitline Cut Structure
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in reducing signal line loads, which can lead to decreased operation speed due to increased integration and memory capacity in three-dimensional structures like vertical NAND flash memory devices.
Innovation Solution
The implementation of a bitline cut structure with first and second vertical conduction paths that connect bitline segments to a page buffer region, reducing bitline loads and enhancing performance by dividing the memory cell array into sub-arrays and using switches to control connections during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration and memory capacity are increased in three-dimensional structures, then storage density is improved, but signal line loads increase causing decreased operation speed
Solution Approach 1:
The bitline is divided into multiple segments (first bitline segments and second bitline segments) that are selectively connected to page buffers through vertical conduction paths. This segmentation reduces the capacitive load on each bitline segment, allowing faster signal transmission while maintaining high memory capacity in the three-dimensional vertical NAND structure.
2Quantity of substance
If integration is increased in vertical NAND flash memory devices, then storage density is improved, but signal line loads increase causing decreased operation speed
Solution Approach 1:
The patent transitions from planar bitline connections to three-dimensional vertical conduction paths that penetrate through the memory cell region. This dimensional change allows bitline segments to be connected to page buffers through vertical paths, reducing horizontal signal line lengths and capacitive loads, thereby improving operation speed while maintaining high vertical storage density.
Data Source
AI summary
A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.