Vertical NAND Bonding Structure for Fewer Channel Contact Defects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for semiconductor devices with improved data storage capacity and reliability, particularly in vertical NAND flash memory devices, to enhance integration density and maintain data storage even when power is not supplied.
Innovation Solution
The semiconductor device incorporates a vertical structure with a first semiconductor structure and a second semiconductor structure connected to the first, featuring conductive patterns, gate electrodes, channel structures, and interconnection structures, including channel holes and channel patterns that enhance electrical connectivity and reduce contact defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical structure with multiple channel holes is used to increase integration density, then data storage capacity is improved, but contact defects between channel structures and conductive patterns increase
Solution Approach 1:
The channel structure is segmented into multiple channel holes (first channel hole, second channel hole) within a single channel structure, allowing separate contact regions for different conductive patterns. This segmentation enables independent optimization of each contact interface, reducing the probability of contact defects while maintaining high integration density.
Solution Approach 2:
The patent transitions from planar contact interfaces to three-dimensional stacked contacts where channel structures extend vertically through multiple conductive patterns. By utilizing the vertical dimension, the patent increases data storage capacity without proportionally increasing contact defect areas, as contacts are distributed across multiple horizontal planes.
2Quantity of substance
If channel structures with multiple channel holes are implemented, then integration density is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The channel structures are formed with predetermined positions and configurations before subsequent conductive patterns are deposited. The first and second channel holes are pre-aligned during the channel structure formation process, establishing a reference framework that guides subsequent manufacturing steps and reduces cumulative alignment errors.
Solution Approach 2:
The channel structures serve as intermediary elements that mediate between the substrate and the overlying conductive patterns. By establishing a stable intermediate layer with defined geometric features, the patent provides a reference framework that simplifies the alignment of subsequent layers and reduces the overall manufacturing precision requirements.
Data Source
AI summary
A semiconductor device may include a first semiconductor structure including a substrate, circuit devices on the substrate, a first interconnection structure electrically coupled to the circuit devices, and a first bonding metal layer on the circuit devices and the first interconnection structure, a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, and the second semiconductor structure including a memory cell substrate including a conductive pattern and an insulating pattern in contact with a side surface of the conductive pattern, gate electrodes stacked and spaced apart from each other below the memory cell substrate, channel structures penetrating the gate electrodes and spaced apart from each other in a first direction, a second interconnection structure below the gate electrodes and the channel structures, a second bonding metal layer below the second interconnection structure, and the second bonding metal layer connected to the first bonding metal layer.