3D Memory Bonding Structure for Dense Vertical NAND Integration
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to size limitations, leading to increased costs and density constraints, which 3D memory architectures aim to address by vertically stacking memory arrays and peripheral devices.
Innovation Solution
A semiconductor apparatus with a silicon substrate, peripheral devices, and interconnect layers, including NAND strings with alternating conductor/dielectric stacks, and a single crystalline silicon layer, allowing for vertical stacking and decoupling of peripheral and array device processing to enhance density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication, then memory density increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory arrays are formed vertically above peripheral devices using multiple alternating conductor/dielectric stacks, enabling memory density scaling without proportionally increasing manufacturing complexity. The 3D stacking approach allows memory cells to be arranged in vertical columns rather than horizontal planes, effectively adding a third dimension to the memory array layout.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but manufacturing cost increases
Solution Approach 1:
By stacking memory arrays vertically in three dimensions above peripheral devices, the patent achieves higher memory density without requiring proportional increases in manufacturing steps. The alternating conductor/dielectric stack formation process uses standard deposition and etching techniques applied in a vertical configuration, avoiding the need for increasingly complex planar processing required by traditional scaling approaches.
3Quantity of substance
If 3D memory architecture is implemented with vertical stacking, then memory density increases, but thermal management becomes more challenging
Solution Approach 1:
The patent separates the memory array formation process into distinct alternating conductor/dielectric stacks that can be independently formed and controlled. This segmentation allows for distributed thermal management where heat can be dissipated through multiple interfaces between conductor and dielectric layers, rather than concentrating thermal load in a single planar structure. The vertical stacking creates multiple thermal pathways for heat dissipation.
4Area of stationary object
If peripheral devices and memory arrays are integrated on the same substrate, then device area is reduced, but thermal budgets and processing constraints conflict
Solution Approach 1:
The patent positions memory arrays vertically above peripheral devices on the substrate, utilizing the vertical dimension to separate memory array processing from peripheral device processing. This spatial separation in the vertical direction allows different thermal budgets and processing conditions to be applied to memory arrays and peripheral devices independently, while still maintaining integration on the same substrate footprint.
Data Source
AI summary
A semiconductor device includes a peripheral circuit, a stacked structure including a first side and a second side along a vertical direction, and alternating conductive layers and first insulating layers, a memory string extending through the stacked structure, a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit, a second insulating layer located at the second side of the stacked structure; and a conductor structure located in the second insulating layer.