Vertical NAND Channel Isolation for Reliable Gate Stack Integration
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Solution Overview
Problem
As the integration density of memory devices increases, manufacturing memory devices with vertical transistor structures becomes increasingly challenging due to the difficulty in stacking multiple gate electrodes while maintaining the integrity of the channel structure.
Innovation Solution
A semiconductor device with a substrate having a memory cell region and a connection region, featuring a channel structure penetrating multiple gate electrodes in the memory cell region and a dummy channel structure in the connection region, along with a first semiconductor layer and an insulating separation structure, which helps in maintaining structural stability and preventing electrical connection between the dummy channel structure and the common source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of gate electrodes stacked in the vertical direction is increased to increase integration density, then the integration density is improved, but the manufacturing difficulty increases
Solution Approach 1:
The device is divided into two distinct regions: a memory cell region with functional channel structures and a connection region with dummy channel structures. This segmentation allows the manufacturing process to address different structural requirements in different areas, facilitating the stacking of multiple gate electrodes while maintaining manufacturability.
Solution Approach 2:
The dummy channel structure acts as an intermediary element in the connection region, providing a placeholder that maintains structural integrity during manufacturing. This intermediary structure enables the vertical stacking of gate electrodes by providing necessary support and alignment references without requiring complex functional channel formations in all areas.
2Quantity of substance
If multiple gate electrodes are stacked vertically to increase integration density, then the integration density is improved, but the channel structure integrity becomes harder to maintain
Solution Approach 1:
Different structural qualities are applied to different regions: the memory cell region contains functional channel structures with specific properties, while the connection region contains dummy channel structures with different properties. This local differentiation allows the vertical gate electrode stacking to be supported in the connection region without compromising the functional integrity of channels in the memory cell region.
Solution Approach 2:
The dummy channel structure serves as a preparatory or cushioning element that is formed beforehand in the connection region. This structure provides structural support and process guidance that cushions against potential integrity issues when stacking multiple gate electrodes vertically, ensuring that the functional channel structures in the memory cell region maintain their integrity.
3Stability of the object's composition
If a dummy channel structure is added in the connection region, then the structural stability is improved, but the device complexity increases
Solution Approach 1:
The dummy channel structure is essentially a copy or replica of the functional channel structure, simplified for use in the connection region. By copying the basic structural form without the full functional complexity, the device gains structural stability while minimizing the increase in overall complexity.
Solution Approach 2:
The dummy channel structure serves multiple functions: it provides structural support for vertical gate electrode stacking, maintains alignment during manufacturing processes, and defines the connection region boundary. This multi-functionality justifies the added structural element by providing several benefits simultaneously rather than requiring separate elements for each function.
Data Source
AI summary
A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.