Vertical NAND Contact Plug Structure to Prevent Gate Shorts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the fabrication of vertical NAND flash memory devices, the formation of contact plugs that penetrate through thin gate electrodes can lead to electrical shorts and increased contact resistance, which are challenging to address effectively.
Innovation Solution
The implementation of a vertical memory device design featuring first and second contact plug structures with metal and barrier patterns, including metal silicide layers, that extend vertically without penetrating through the gate electrodes, thereby reducing contact resistance and preventing electrical shorts between gate electrodes on different levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to penetrate through thin gate electrodes, then contact resistance is reduced, but electrical shorts occur between gate electrodes on different levels
Solution Approach 1:
A barrier pattern is introduced as an intermediary layer between the contact plug and the gate electrode. This barrier pattern prevents direct contact between the conductive material and the gate electrode, thereby preventing electrical shorts while still allowing for effective electrical connection through controlled contact regions.
Solution Approach 2:
The contact plug structure is segmented into multiple functional regions: a lower contact region that contacts the gate electrode, a barrier pattern layer that prevents unwanted electrical connection, and an upper extension region that provides mechanical support and electrical connection to upper layers. This segmentation allows each region to perform its specific function without interfering with others.
2Quantity of substance
If gate electrode thickness is reduced, then device density is increased, but contact plugs may penetrate through the gate electrodes
Solution Approach 1:
The barrier pattern serves as a mediator that allows the use of thinner gate electrodes without risking penetration. By introducing this intermediate layer, the design can maintain reduced gate electrode thickness for higher density while the barrier pattern prevents the contact plug from penetrating through the thin gate electrode structure.
Solution Approach 2:
The barrier pattern is formed in advance before the contact plug is deposited. This preliminary action of creating the barrier layer ensures that when the contact plug is subsequently formed, it cannot penetrate through the gate electrode, thus preventing manufacturing defects before they occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical characteristics by reducing contact resistance and preventing electrical shorts, ensuring reliable operation of the vertical memory device.
Implementation Method 1
a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern... The first contact plug structure contacting a corresponding one of the first gate electrodes
Implementation Method 2
a first barrier pattern covering a lower surface and a sidewall of the first metal pattern... preventing electrical shorts between gate electrodes on different levels
Data Source
AI summary
A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.