3D Vertical NAND With Continuous Control Gates
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Solution Overview
Problem
Existing three-dimensional vertical NAND string devices, such as TCAT and P-BiCS, have suboptimal density due to the presence of trenches between adjacent vertical NAND strings, which increases the pitch between memory holes and reduces array efficiency by more than 50%.
Innovation Solution
The implementation of monolithic three-dimensional NAND strings with continuous control gate electrodes that do not have air gaps or dielectric-filled trenches, allowing for a denser array configuration by eliminating word line trenches and optimizing the formation of select gate levels and memory device levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trenches are introduced between adjacent vertical NAND strings, then select gate separation is achieved, but device density decreases and pitch between memory holes increases
Solution Approach 1:
The patent transitions from planar separation to vertical separation by forming trenches that extend downward between select gates while maintaining continuous control gates at upper levels. This dimensional approach allows select gate isolation without compromising overall array density, as the trenches are confined to specific vertical zones rather than separating entire string structures.
Solution Approach 2:
The patent segments the trench structure into localized regions between specific select gates (e.g., first and second select gates) rather than continuous separation throughout the entire vertical NAND string. This selective segmentation achieves necessary electrical isolation while minimizing impact on overall device density and maintaining continuity of control gates in memory device levels.
2Quantity of substance
If continuous control gates are formed without trenches, then device density increases, but select gate isolation becomes difficult
Solution Approach 1:
The patent segments the control gate structure into distinct functional zones: continuous control gates in memory device levels for high density, and separated select gates in select gate levels for proper isolation. This segmentation allows each zone to optimize its function without compromising the other.
Solution Approach 2:
The patent uses vertical dimensionality to resolve the contradiction by forming trenches that extend downward from upper levels to separate select gates, while control gates remain continuous at upper memory device levels. This three-dimensional arrangement maintains both density and isolation requirements simultaneously.
3Stability of the object's composition
If trenches are filled with dielectric material, then structural support is provided, but array efficiency decreases by more than 50%
Solution Approach 1:
The patent applies dielectric filling selectively in localized trench regions between select gates rather than throughout the entire array structure. This local application provides necessary structural support and electrical isolation only where required, minimizing the impact on active memory areas and preserving array efficiency.
Solution Approach 2:
The patent segments the dielectric fill into confined regions within trenches between specific select gates, rather than using dielectric material throughout the entire vertical NAND structure. This segmentation ensures structural support is provided only where needed for select gate separation, maintaining high array efficiency.
Data Source
AI summary
A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.