Vertical NAND Contact Plug Layout Using CSL Overlap
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Solution Overview
Problem
In vertical NAND flash memory devices with a cell over periphery (COP) structure, the formation of contact plugs to connect lower peripheral circuits to upper wirings requires additional space and process steps, leading to increased complexity and size.
Innovation Solution
A vertical memory device design where the lower contact plug is formed under the common source line (CSL) and overlaps with it, eliminating the need for additional space and simplifying the process, thus reducing the device size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a contact plug is formed at the outskirts of a memory cell array to connect lower peripheral circuits to upper wirings, then electrical connection is achieved, but additional space and process steps are required, increasing device size and complexity
Solution Approach 1:
The contact plug formation process is merged with the existing common source line formation process. The contact plug and CSL share the same opening formation step through the gate electrode structure, eliminating the need for separate contact plug formation processes and reducing overall process complexity.
Solution Approach 2:
The opening formed through the gate electrode structure serves multiple functions: it acts as both the contact plug opening for electrical connection and the CSL opening for the common source line. This multi-functional design eliminates the need for separate openings and reduces device complexity.
2Reliability
If a contact plug is formed at the outskirts of a memory cell array to connect lower peripheral circuits to upper wirings, then electrical connection is achieved, but additional space is needed, increasing device size
Solution Approach 1:
The contact plug is positioned in the vertical dimension by extending through the gate electrode structure, allowing it to connect lower peripheral circuits to upper wirings without requiring additional horizontal space at the outskirts of the memory cell array.
Solution Approach 2:
The contact plug and common source line share the same opening and formation process, allowing both structures to be created simultaneously without requiring additional space for separate contact plug formation at the device outskirts.
3Reliability
If additional process steps are used to form the contact plug, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The contact plug formation is merged with the CSL formation process, using the same opening formation step through the gate electrode structure. This eliminates additional manufacturing steps and simplifies the overall fabrication process.
Solution Approach 2:
The same opening formation process serves dual purposes: creating the contact plug opening for electrical connection and the CSL opening for the common source line. This multi-functional approach reduces the number of manufacturing steps required.
Data Source
AI summary
A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.