Vertical NAND Dummy Channel Layout for Pad Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile memory devices with planar transistor structures face limitations in increasing storage capacity and integration density, necessitating the development of vertical channel structures to enhance reliability and integration.
Innovation Solution
A vertical type non-volatile memory device is designed with a substrate featuring a cell array and extension area, including vertical channel structures, dummy channel structures, gate electrode layers, and interlayer insulation layers, along with a specific layout and manufacturing method that involves optical proximity correction to optimize the shape and placement of dummy channel structures in the electrode pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar transistor structures are used, then manufacturing process is simple, but storage capacity and integration density cannot be increased
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) channel structures, utilizing the vertical dimension to increase integration density and storage capacity while maintaining manufacturability through adapted fabrication processes
2Productivity
If vertical channel structures are introduced to increase integration density, then storage capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms mandrel structures and sacrificial layers before creating the final vertical channel structures, using preliminary structures to guide and enable precise formation of the vertical channels through controlled etching and material removal processes
3Reliability
If dummy channel structures are added in electrode pad area, then reliability improves, but device complexity increases
Solution Approach 1:
The patent places dummy channel structures specifically in the electrode pad area rather than uniformly across the device, providing localized reliability enhancement where electrical connections are critical, while minimizing overall structural complexity
Data Source
AI summary
A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.