Vertical NAND Flash Memory Device With Merged Gate Lines
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Solution Overview
Problem
Contemporary integrated circuit devices face challenges in increasing data storage capacity while maintaining efficient read, write, and erase operations, particularly in vertical memory devices where the number of stacked memory cells needs to be increased.
Innovation Solution
The integration of a vertical NAND flash memory device with a configuration that includes channel structures extending vertically from a substrate, memory cell strings disposed along these channel structures, and a specific arrangement of gate lines and driving transistors, allowing for efficient control of erase and selection operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased to increase data storage capacity, then the data storage capacity is improved, but the device complexity increases
Solution Approach 1:
Multiple gate lines (first erase control line, second erase control line, first string selection line, second string selection line) are merged and commonly connected to a single driving transistor. This consolidation reduces the number of driving transistors needed, thereby reducing device complexity while maintaining the capability to control multiple memory cell strings for increased data storage capacity.
Solution Approach 2:
The commonly connected driving transistor serves multiple functions by controlling multiple gate lines simultaneously. This multi-functional approach allows a single transistor to manage erase operations and string selection across multiple memory cell strings, reducing the overall transistor count and device complexity while supporting expanded storage capacity.
2Quantity of substance
If the number of stacked memory cells is increased to increase data storage capacity, then the data storage capacity is improved, but the control efficiency deteriorates
Solution Approach 1:
Multiple gate lines are merged and commonly connected to a single driving transistor, enabling centralized control of multiple memory cell strings. This merging simplifies the control architecture, maintaining control efficiency even as the number of stacked memory cells and data storage capacity increases.
Solution Approach 2:
The driving transistor configured with common connections to multiple gate lines performs multiple control functions simultaneously. This multi-functionality allows efficient management of erase operations and string selection across numerous memory cell strings, preserving control efficiency while scaling storage capacity.
Data Source
AI summary
An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.