Vertical NAND Memory Cell Programming Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in memory devices with vertical structures, such as NAND flash memory, is the occurrence of charge leakage and other phenomena that introduce uncertainty and reduce reliability during programming and sensing operations, necessitating alternative methods for operating these devices.
Innovation Solution
The solution involves configuring memory cells on substantially vertical semiconductor pillars, where select gates are formed adjacent to the pillars and coupled in series with memory cells, and applying specific voltage waveforms to inhibit programming of untargeted cells by maintaining the pillar regions in a floating state, thereby preventing charge accumulation and ensuring accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in vertical pillars to increase memory density, then memory density is improved, but charge leakage and operational reliability deteriorate
Solution Approach 1:
The vertical pillar structure is segmented into multiple discrete memory cells along the vertical axis, with select gates positioned at different heights. This segmentation allows independent control of charge injection for each memory cell, preventing charge leakage between adjacent cells while maintaining high density.
Solution Approach 2:
Different regions of the vertical pillar structure are assigned different functional properties: charge-storage structures are positioned at specific locations adjacent to the pillar, and select gates are placed at different heights with different control voltages applied. This local differentiation enables precise control of programming operations and prevents unwanted charge injection in unselected cells.
2Manufacturing precision
If select gates are positioned at different heights on vertical pillars, then programming precision is improved, but device complexity increases
Solution Approach 1:
Multiple select gates are merged into a single vertical pillar structure, sharing the same physical substrate and charge-storage region. This integration reduces the overall device footprint and manufacturing complexity compared to using separate structures for each select gate, while still enabling independent control through different voltage signals.
Solution Approach 2:
The select gates are arranged in the vertical dimension rather than horizontally, allowing multiple gates to be stacked along the height of the pillar. This vertical stacking enables precise control of different memory cells along the vertical axis without increasing lateral device complexity.
3Quantity of substance
If charge-storage structures are positioned adjacent to vertical pillars, then memory cell capacity is improved, but charge leakage increases
Solution Approach 1:
The charge-storage structures are extracted from the traditional planar configuration and repositioned adjacent to the vertical pillar structure. This spatial separation isolates the charge storage function from the channel region, increasing capacity while the vertical pillar acts as a barrier to prevent charge leakage to adjacent cells.
Solution Approach 2:
The vertical pillar structure serves as an intermediary between the charge-storage structures and the channel region. It provides a controlled interface that allows charge injection when needed while preventing unwanted charge leakage, thus mediating between capacity requirements and leakage prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and accuracy of memory operations by preventing unintended programming and maintaining the integrity of data storage in vertical memory structures, thereby improving memory device performance and reliability.
Implementation Method 1
each memory cell comprising a channel region, a control gate, a first diffusion region, and a second diffusion region. The first diffusion region may be coupled to the source, the second diffusion region may be coupled to the bit line, and the control gate may be coupled to the word line.
Implementation Method 2
Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena
Data Source
AI summary
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.