Ultrahigh Density Vertical NAND Memory Device
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional vertical NAND strings have limitations, such as providing only one bit per cell and requiring complex and time-consuming processes for active region formation, which results in conical shapes that are difficult to achieve.
Innovation Solution
A method for forming monolithic three-dimensional NAND strings by creating a stack of alternating conductive or semiconductor control gate material and insulating material layers over a substrate, etching to form openings, and selectively etching to create recesses for discrete charge storage segments, tunnel dielectrics, and semiconductor channels, allowing for multiple bits per cell and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertical NAND string processes are used, then one bit per cell is achieved, but memory density is limited
Solution Approach 1:
The charge storage region is divided into multiple discrete charge storage segments along the vertical channel, enabling multiple bits to be stored in a single cell. This segmentation of the floating gate into distinct segments allows independent programming and reading of multiple bits within the same physical cell structure, thereby increasing memory density without proportionally increasing device complexity.
2Ease of manufacture
If repeated sidewall spacer formation and substrate etching are used, then active regions are formed, but the process is time-consuming and complex
Solution Approach 1:
The method performs preliminary actions by forming the complete stack structure including alternating insulating and conductive layers before creating openings and defining active regions. This preliminary formation of the layered structure simplifies subsequent processing steps and reduces the overall manufacturing cycle time compared to conventional approaches that require repeated spacer formation and etching.
Solution Approach 2:
The invention transitions from planar processing to vertical three-dimensional processing by forming stacked layers and vertical channels. This dimensional change allows for more efficient use of substrate area and simplifies the formation of active regions through vertical etching rather than repeated lateral spacer formation, thereby reducing manufacturing complexity and time.
3Manufacturing precision
If conventional etching processes are used, then conical active region shapes are formed, but achieving precise shapes is difficult
Solution Approach 1:
The method forms preliminary sacrificial structures and masking layers before etching the active regions. These preliminary structures serve as precise templates that define the desired shape of the vertical channels and active regions, enabling accurate shape control through subsequent etching processes without requiring complex real-time etching control.
Solution Approach 2:
Sacrificial structures are introduced as intermediary elements that facilitate the formation of precise active region shapes. These sacrificial layers are deposited, patterned, and etched to create the desired geometry, then removed to leave behind the precisely shaped active regions. This intermediary approach simplifies the etching process while achieving high manufacturing precision.
Data Source
AI summary
Monolithic three dimensional NAND string includes a semiconductor channel having a U-shaped pipe shape. A plurality of control gate electrodes having a strip shape extends substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. A cut area separates the plurality of control gate electrodes in a direction substantially perpendicular to the major surface of the substrate. A blocking dielectric is located in contact with the plurality of control gate electrodes, a charge storage region located in contact with the blocking dielectric and a tunnel dielectric is located between the charge storage region and the semiconductor channel.