Vertical NAND Flash Memory Pillar Select Gate Transistor Design
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Solution Overview
Problem
The manufacturing of NAND-type flash memories with vertical memory cells faces challenges in achieving finer patterns and easier processing due to the difficulty in removing charge storage layers from select gate transistors on the semiconductor substrate, leading to complex manufacturing techniques and height differences between memory cell arrays and peripheral circuits.
Innovation Solution
The design includes pillar-shaped semiconductor layers with memory cells and select gate transistors arranged vertically, where the source/drain regions are formed in the semiconductor substrate, allowing for easier processing of select gate transistors as MIS structures and reducing the complexity of manufacturing by eliminating the need for high-level techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cells are designed with MONOS structure to simplify manufacturing, then the manufacturing process becomes easier, but the select gate transistor on the bottom end cannot have its charge storage layer removed, requiring negative potential control circuits
Solution Approach 1:
The charge storage layer is selectively removed from the bottom select gate transistor region, extracting the problematic component only where needed. This allows the bottom select gate transistor to function as a simple MIS transistor without requiring complex negative potential control, while memory cells retain the MONOS structure for simplified manufacturing.
Solution Approach 2:
Different structures are applied to different regions: the bottom select gate transistor uses a MIS structure (without charge storage layer) for simple threshold voltage control, while memory cells use the MONOS structure for manufacturing simplicity. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Manufacturing precision
If memory cell array region is designed with vertical structure to increase integration density, then memory capacity increases, but a large step height is created making peripheral transistor processing difficult
Solution Approach 1:
The memory cell structure transitions from planar to vertical stacking, utilizing the third dimension (height) to increase integration density. Meanwhile, peripheral transistors remain in the planar domain at the substrate level, avoiding the step height problem while maintaining high memory capacity.
Solution Approach 2:
The chip is segmented into two functional zones: a vertical memory cell array region for high-density storage and a planar peripheral circuit region for control functions. This segmentation allows each region to be optimized independently, with peripheral transistors processed at the lower substrate level avoiding interference from the vertical memory structure.
3Reliability
If etching process is performed on polysilicon film on side surface of groove to achieve U-shaped memory cell structure, then memory cell functionality is achieved, but high degree of manufacturing techniques is required
Solution Approach 1:
Instead of performing complex side-surface etching of polysilicon, the invention uses a simplified planar process where polysilicon is deposited and patterned on the flat substrate surface. The vertical memory structure is then formed by stacking subsequent layers, copying the essential functionality through a much simpler manufacturing sequence.
Solution Approach 2:
The conventional approach builds the memory structure by etching upward from the substrate. The invention inverts this approach by first creating the complete vertical stack through deposition and planar processing, then defining the final structure through simpler surface patterning, avoiding the need for complex side-surface etching.
Data Source
AI summary
A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.