Vertical NAND Programming Sequence for Program Disturb Suppression
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Solution Overview
Problem
In vertical NAND string architectures, the increased resistance of channel regions makes it difficult to boost the voltage level of the channel region prior to applying a programming pulse, leading to unintended threshold voltage changes in adjacent memory cells during programming, known as program disturb.
Innovation Solution
Employing gate-induced drain leakage (GIDL) to facilitate voltage boosting in the channel regions of unselected memory cells, maintaining select gates in a deactivated state during the data line voltage rise, and using a higher initial voltage level to induce GIDL current, thereby enhancing the voltage level of the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical NAND string architecture is used to increase memory density, then memory capacity is improved, but channel region resistance increases making voltage boosting difficult
Solution Approach 1:
The patent applies preliminary action by boosting the channel region voltage to a high level (e.g., 5V or higher) before applying the programming pulse to the memory cell. This pre-boosting ensures that when the programming pulse is applied, the voltage differential across the gate stack of unselected memory cells remains insufficient to cause threshold voltage changes, thereby preventing program disturb while enabling effective programming of selected cells in the high-resistance vertical architecture
2Reliability
If channel voltage is boosted to inhibit programming of adjacent memory cells, then program disturb is prevented, but unintended threshold voltage changes may still occur if boosting is insufficient
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the channel region voltage to a sufficiently high level (e.g., 5V or higher) during programming operations. This voltage parameter adjustment creates an adequate voltage differential that prevents both program disturb and unintended threshold voltage changes in unselected memory cells, while allowing proper programming of selected cells
3Reliability
If higher voltage levels are applied during programming to ensure proper programming, then programming reliability is improved, but program disturb in adjacent cells increases
Solution Approach 1:
The patent applies local quality by creating different voltage conditions in different regions: the channel region is boosted to a high voltage level to prevent program disturb in unselected cells, while the control gate of the selected memory cell receives the programming pulse at the appropriate voltage level. This localized voltage control ensures that each region experiences the voltage conditions necessary for its specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively inhibits unintended threshold voltage changes in unselected memory cells, improving programming efficiency and reducing program disturb issues in vertical memory arrays.
Implementation Method 1
Employing gate-induced drain leakage (GIDL) to facilitate voltage boosting in the channel regions of unselected memory cells, maintaining select gates in a deactivated state during the data line voltage rise, and using a higher initial voltage level to induce GIDL current, thereby enhancing the voltage level of the channel regions
Data Source
AI summary
Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.