Vertical Gate Stacked NAND Row Decoder for Sub-Block Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in designing and manufacturing vertical NAND flash memory devices is to reduce write amplification while maintaining the ability to read and program individual strings and pages, without increasing cell area or bit costs, and addressing technical limitations in stacked memory architectures.
Innovation Solution
A three-dimensional vertical gate NAND flash memory device with separate source lines and a decoding scheme that allows for sub-block erase operations, using a dedicated source line structure and string select structure to reduce the erase block size-to-page size ratio, and a row decoder circuit to select erase blocks for efficient operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical gate stacked NAND architecture is used to increase memory density, then chip area per data bit is reduced, but write amplification increases and erase block size becomes large
Solution Approach 1:
The patent divides the memory array into multiple independently controllable source line structures, where each source line structure is paired with a specific string select structure to form separate erase blocks. This segmentation allows selective erasure of smaller blocks rather than erasing the entire large block, thereby reducing write amplification while maintaining the high-density vertical stacked architecture.
2Productivity
If erase block size is reduced to improve write amplification, then write amplification performance improves, but cell area or bit costs increase
Solution Approach 1:
The patent transitions from a two-dimensional planar architecture to a three-dimensional vertical gate stacked architecture. By stacking multiple memory layers vertically and introducing separate source line structures in the vertical dimension, the patent achieves smaller effective erase blocks without increasing the lateral cell area, thus improving write amplification while maintaining manufacturing cost efficiency.
3Adaptability or versatility
If separate source line structures are introduced to enable sub-block erase operations, then erase block granularity is improved, but device complexity increases
Solution Approach 1:
The patent designs the separate source line structures to serve multiple functions: they act as control lines for selecting specific erase blocks, provide electrical connections for program and read operations, and enable independent voltage control for different memory regions. This multi-functionality reduces the need for additional dedicated control mechanisms, thereby limiting the increase in device complexity while achieving fine-grained erase block control.
Data Source
AI summary
A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.