Vertical NAND Memory Stack Sequential Etching Alignment
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Solution Overview
Problem
The challenge in three-dimensional vertical NAND (VNAND) devices is the limited number of stacked memory layers due to hard mask thickness and reactive ion etching (RIE) energy constraints, which restricts the aspect ratio of memory openings and leads to channel discontinuity and increased resistance, affecting read performance and thermal budgets.
Innovation Solution
The method involves forming a memory stack with separate etching of memory opening portions using thin hard masks and landing pads to align misaligned memory opening portions, reducing channel discontinuity and increasing the number of stacked memory layers by sequential etching, while adding a semiconductor landing pad to connect adjacent channel portions and manage resistance impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thin hard masks are used for sequential etching of memory opening portions, then the number of stacked memory layers can be increased, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
Landing pads are introduced as intermediary structures between sequential memory opening etching steps. These landing pads serve as alignment references and connection structures that bridge misaligned opening portions, enabling the formation of continuous channels through multiple etching stages while maintaining precise positional relationships.
Solution Approach 2:
The memory opening formation process is segmented into multiple sequential etching steps, each creating a portion of the final opening. This segmentation allows the use of thin hard masks for each individual step while the cumulative effect achieves the desired deep opening through multiple stacked memory layers, with landing pads connecting the segmented portions.
2Productivity
If sequential etching is used to increase stacked memory layers, then device density improves, but channel discontinuity increases causing performance degradation
Solution Approach 1:
Landing pads function as intermediary connection structures that physically bridge the channel portions formed in sequential etching steps. This ensures continuous electrical conduction through the channel despite the multi-step fabrication process, preventing channel discontinuity while enabling increased device density through additional stacked layers.
Solution Approach 2:
Landing pads are formed in advance before the sequential etching of memory opening portions. This preliminary action establishes the connection structures beforehand, ensuring that when the etching steps create the channel portions, the landing pads are already in position to maintain channel continuity and prevent discontinuities.
3Quantity of substance
If more stacked memory layers are formed, then storage capacity increases, but resistance in continuous memory openings increases affecting read performance
Solution Approach 1:
Landing pads serve as intermediary low-resistance connection structures between the channel portions formed in sequential etching steps. By providing highly conductive pathways at the interfaces between etched portions, landing pads reduce the cumulative resistance that would otherwise increase with more stacked memory layers, thereby maintaining read performance while increasing storage capacity.
4Temperature
If sequential etching with thin hard masks is employed, then thermal budget is reduced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into multiple sequential steps, each using thin hard masks that can be formed and etched at lower temperatures. This segmentation of the etching process into manageable portions allows the use of thin masks throughout, reducing the cumulative thermal budget compared to single-step etching with thick masks, while the added process steps are managed through systematic process integration.
Data Source
AI summary
A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.