Vertical NAND Staircase Wiring Layout for Dishing Reduction
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Solution Overview
Problem
Vertical NAND flash memory devices face challenges in forming a flat upper surface of the insulating interlayer due to dishing defects, which occur as the stacking height of memory cells increases, leading to process defects and difficulties in accurately forming the stepped shape of the wiring connection structure.
Innovation Solution
A vertical memory device design that includes a substrate with a cell stacked structure and a wiring connection structure featuring a staircase and dummy staircase configuration, where the first and second staircase structures are spaced apart, and the dummy staircase structure has symmetrical steps, allowing for accurate formation of the insulating interlayer and reducing dishing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacking height of memory cells is increased, then the storage capacity is improved, but the step difference between the cell stacked structure and the pad structure increases, causing dishing defects in the insulating interlayer
Solution Approach 1:
The pad structure is segmented into multiple stepped levels (first pad level, second pad level, third pad level) that correspond to different heights of the cell stacked structure. This segmentation allows each pad level to contact the cell stacked structure at a specific height, distributing the step difference across multiple levels rather than having a single large step, thereby preventing dishing defects in the insulating interlayer.
Solution Approach 2:
The solution transitions from a single-level pad structure to a multi-level stepped pad structure in the vertical dimension. By creating multiple pad levels at different heights, the design accommodates the increased stacking height of memory cells while maintaining proper electrical contact and preventing dishing defects in the insulating interlayer.
2Quantity of substance
If the stacking height of memory cells is increased, then the storage capacity is improved, but it becomes difficult to form the insulating interlayer with a flat upper surface
Solution Approach 1:
The pad structure is divided into multiple stepped levels that match the heights of different cell stacked structures. This segmentation creates a阶梯状 (stepped) configuration where each pad level can be planarized independently, making it easier to form the insulating interlayer with a flat upper surface even when the cell stacking height is increased.
Solution Approach 2:
The stepped pad structure is formed in advance before depositing the insulating interlayer. By pre-configuring the pad structure with multiple levels that correspond to the cell stacked structure heights, the subsequent formation of the insulating interlayer becomes easier, as the surface to be covered already has a controlled stepped topology that facilitates planarization.
3Reliability
If the wiring connection structure is formed with a stepped shape to contact side walls of the cell stacked structure, then the electrical connection is improved, but the process complexity increases due to the need to accurately form multiple stepped levels
Solution Approach 1:
The pad structure and the wiring connection structure are merged into a single integrated stepped structure. The first pad level, second pad level, and third pad level are formed as part of the same continuous structure that contacts the side walls of the cell stacked structure. This merging reduces process complexity by eliminating the need for separate formation steps for pads and wiring connections.
Solution Approach 2:
The stepped pad structure serves multiple functions: it provides electrical connection to the cell stacked structure at different heights, acts as a wiring connection structure, and facilitates the formation of the insulating interlayer. This multi-functionality reduces the overall device complexity by consolidating multiple structural elements into a single universal structure.
Data Source
AI summary
A vertical memory device includes a cell stacked structure, a wiring connection structure, and a first insulating interlayer. The cell stacked structure may include insulation layers and gate patterns repeatedly and alternately stacked on a first region of a substrate. The wiring connection structure may contact side walls of the cell stacked structure. The wiring connection structure may include a first staircase structure having one side of a stepped shape, a second staircase structure having one side of a stepped shape and disposed below the first staircase structure, and a first dummy staircase structure between the first and second staircase structures. The first and second staircase structures may be spaced apart from each other in the first direction, and both sides in the first direction of the first dummy staircase structure may have stepped shapes. The first insulating interlayer may be on the substrate to cover the wiring connection structure.