Vertical NAND Charge Storage Segmentation Against Charge Migration
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Solution Overview
Problem
Vertical NAND flash memory devices face challenges with deteriorating charge retention characteristics due to increased charge transfer and reduced height of memory cells, which affect the reliability and efficiency of data storage.
Innovation Solution
A vertical nonvolatile memory device design featuring a structure with separated charge storage layers and charge tunneling layers, utilizing semiconductor materials doped with high concentrations of dopants, and a manufacturing process that forms charge blocking and tunneling layers through oxidation, enhancing charge retention and reducing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to achieve higher integration, then storage capacity is improved, but charge transfer between memory cells increases and charge retention characteristics deteriorate
Solution Approach 1:
The charge storage layer is divided into multiple discrete segments along the vertical channel, with each segment corresponding to a specific memory cell. These segmented charge storage layers are separated by isolation layers that prevent charge transfer between adjacent memory cells, thereby maintaining charge retention characteristics even as the number of stacked layers increases for higher storage capacity.
Solution Approach 2:
Isolation layers are introduced as intermediary structures between adjacent charge storage layers of different memory cells. These isolation layers act as barriers that block charge transfer while allowing the memory cells to function independently, thus resolving the charge retention issue caused by increased stacking.
2Productivity
If the height of memory cells is decreased to increase the number of stacked layers, then integration is improved, but charge retention characteristics worsen due to increased charge transfer
Solution Approach 1:
By segmenting the charge storage layer into discrete units separated by isolation layers, each memory cell maintains its charge independently even when cell height is reduced. This segmentation prevents the charge transfer that would otherwise occur in compact, high-density stacked structures.
Solution Approach 2:
The isolation layers are strategically positioned at specific locations between charge storage layers to provide localized charge blocking. This allows different regions of the memory structure to have different properties - the charge storage regions maintain high density while the isolation regions provide charge confinement, enabling both high integration and good charge retention.
3Ease of manufacture
If conventional charge storage layers are used without high dopant concentration, then manufacturing is simpler, but charge retention characteristics are insufficient
Solution Approach 1:
The dopant concentration in the charge storage layer is increased to a specific range (1×10^18 to 1×10^20 atoms/cm³) to optimize charge retention characteristics. This parameter change enhances the ability of the charge storage layer to retain charges without requiring complex manufacturing processes, as it can be achieved through standard ion implantation or in-situ doping techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves charge retention characteristics and reduces process costs by minimizing charge migration between memory cells, maintaining high integration and low power consumption.
Implementation Method 1
The plurality of charge storage layers include a semiconductor material doped with a dopant at a doping concentration of 10^18 atoms/cm³ or higher
Implementation Method 2
at least one charge tunneling layer adjacent to the channel layer in a second direction intersecting the first direction
Implementation Method 3
a manufacturing process that forms charge blocking and tunneling layers through oxidation
Data Source
AI summary
A nonvolatile memory device includes a plurality of cell strings each including a channel layer extending in a first direction, at least one charge tunneling layer adjacent to the channel layer in a second direction intersecting the first direction, a plurality of charge storage layers adjacent to the at least one charge tunneling layer in the second direction, the plurality of charge storage layers spaced apart in the first direction, a plurality of charge blocking layers adjacent to respective charge storage layers of the plurality of charge storage layers in the second direction, a plurality of gate electrodes adjacent to respective charge blocking layers of the plurality of charge blocking layers in the second direction, and a plurality of separation layers configured to isolate the plurality of charge storage layers, the plurality of charge blocking layers, and the plurality of gate electrodes in the first direction.