Vertical Nano-Pillar FET Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional 2-D integrated circuits face limitations such as susceptibility to electro-static discharge, leakage currents, and parasitic capacitance issues due to their planar fabrication constraints.
Innovation Solution
The development of nano-pillar field-effect transistor (FET) structures with a vertical device structure, vertically displaced source and drain regions, and the use of layer transfer techniques to improve transistor performance by reducing RON resistance, enhancing switching speed, and minimizing parasitic characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 2-D planar MOSFET structures are used, then fabrication is simpler and manufacturing is easier, but parasitic capacitance increases and electrostatic discharge susceptibility increases
Solution Approach 1:
The patent transitions from conventional 2-D planar MOSFET structures to 3-D vertically stacked nanowire FET structures. Multiple nanowire channels are stacked vertically between source and drain regions, creating a gate-all-around configuration that surrounds each nanowire channel. This vertical stacking enables improved electrostatic control and reduced parasitic capacitance while maintaining manufacturing feasibility through adapted fabrication processes.
Solution Approach 2:
The gate structure completely surrounds each nanowire channel in a gate-all-around configuration, with multiple such structures nested vertically. The gate wraps around the channel from all sides, providing maximum electrostatic control. This nested arrangement reduces parasitic capacitance by optimizing the electrical field distribution and isolating adjacent structures.
2Device complexity
If conventional 2-D planar MOSFET structures are used, then device structure is simpler, but electrostatic discharge susceptibility increases and leakage currents increase
Solution Approach 1:
The patent employs vertically stacked nanowire channels arranged in multiple tiers between source and drain regions. This 3-D configuration provides superior electrostatic control compared to planar structures, as the gate-all-around configuration surrounds each channel from all sides, effectively suppressing electrostatic discharge and reducing leakage currents through enhanced electric field management.
Solution Approach 2:
The structure utilizes composite material arrangements with alternating layers of semiconductor nanowire channels and gate dielectric materials. Different semiconductor materials (e.g., Si, Ge, III-V compounds) may be used for different nanowire channels to optimize performance for specific applications, while the gate dielectric provides electrical isolation and controls the electrostatic properties of the device.
3Ease of manufacture
If gate contact overlies source and drain contacts in conventional 2-D MOSFETs, then fabrication is easier, but parasitic capacitance problems increase
Solution Approach 1:
The patent implements a vertical stacking architecture where source, drain, and gate contacts are arranged in different vertical tiers rather than overlapping in the same plane. The gate contact is positioned at a different vertical level than the source and drain contacts, eliminating the parasitic capacitance issues associated with overlapping contacts while maintaining straightforward fabrication through vertical alignment processes.
Data Source
AI summary
Nano-pillar field-effect transistor (FET) structure that include one or more of the following characteristics: vertical device structure and vertical current flow; vertically displaced source and drain regions; different nanowire/nanosheet geometries and dimensions for different nano-pillar embodiments; and/or body contacts made through wide nano-pillar structures. In addition, by utilizing layer transfer techniques, direct access to drain contacts of a nano-pillar FET structure is available, which enables a significant improvement in transistor performance (e.g., lower RON resistance, faster switching speed). An additional advantage of the novel nano-pillar FET structures is that available top and bottom contacts may be used in various 3-D integrated circuit structures, such as by using layer transfer and/or hybrid bonding.