Vertical Nanosheet Transistor With Backside Source/Drain Contacts
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating vertical nanosheet transistors with backside power distribution networks (BSPDN) due to the need for effective source/drain contact formation in reduced footprints, which is not adequately addressed by existing technologies.
Innovation Solution
A semiconductor structure is developed with vertical nanosheet transistors featuring a metal gate surrounding the nanosheets, sidewall and inner spacers, and backside source/drain contacts, along with a method involving sacrificial gate replacement and epitaxial growth of source/drain regions, allowing for efficient integration with BSPDN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical nanosheet transistors are integrated with backside power distribution network, then device density is enhanced, but source/drain contact formation becomes more difficult
Solution Approach 1:
The patent implements backside source/drain contact formation instead of conventional frontside contact formation. The method involves forming openings through the substrate from the backside to contact the source/drain regions, thereby inverting the traditional contact formation approach and enabling integration with BSPDN while maintaining manufacturing feasibility
Solution Approach 2:
The patent transitions from planar contact formation to three-dimensional contact formation by accessing the source/drain regions from the backside of the substrate. This dimensional change allows simultaneous achievement of high device density through vertical nanosheet structure and manageable contact formation through backside access
2Productivity
If footprint is reduced to accommodate smaller node, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming placeholders in the substrate before forming the vertical nanosheet transistor structure. These placeholders define the future contact locations, enabling precise alignment of backside contacts with source/drain regions even as footprint is reduced. The placeholders serve as alignment references throughout the subsequent fabrication steps
Solution Approach 2:
The patent introduces placeholders as intermediary structures that mediate between the substrate and the source/drain regions. These placeholders facilitate precise contact formation by providing defined locations for opening formation, thereby reducing manufacturing precision requirements despite reduced footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable backside source/drain contacts, enhancing device density and integration with BSPDN, thus addressing the challenges of scaling and footprint reduction in semiconductor manufacturing.
Implementation Method 1
epitaxially growing a source/drain region from the end surfaces of the set of vertical nanosheets
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a vertical nanosheet transistor, the vertical nanosheet transistor includes a first and a second vertical nanosheet horizontally separated by a gap; a metal gate surrounding the first and the second vertical nanosheet respectively at a top, a bottom, and a left and a right sidewall thereof; and a first and a second source/drain region in contact with the first and the second vertical nanosheet; where the first and the second vertical nanosheet and the gap between the first and the second vertical nanosheet are vertically above a raised portion of a backside inter-level dielectric layer. A method of manufacturing the semiconductor structure is also provided.