Vertical Nanosheet Transistor Layout With Backside Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating three-dimensional designs, such as vertical transistors, due to issues in device density, performance, and cost, particularly in achieving efficient interconnections and reducing capacitance in nanometer technology process nodes.
Innovation Solution
A semiconductor arrangement featuring a vertical unit cell architecture with nanosheets and backside interconnections, allowing for flexible interconnection of transistors and reducing capacitance compared to finFET devices, using techniques like shallow trench isolation, patterned etching, and replacement gate structures to form efficient logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional designs such as vertical transistors are implemented to increase device density, then device density and performance are improved, but fabrication complexity and interconnection challenges increase
Solution Approach 1:
The transistor structure is segmented into multiple thin nanosheets stacked vertically, with each nanosheet forming a conducting channel. This segmentation allows for better control of current flow and reduced leakage while maintaining high device density, addressing the fabrication challenges of three-dimensional designs
Solution Approach 2:
The invention transitions from two-dimensional planar transistors to three-dimensional vertical nanosheet transistors by stacking multiple conducting channel nanosheets vertically. This dimensional change enables higher device density and improved performance while managing fabrication complexity through the specific nanosheet architecture
2Ease of manufacture
If conventional interconnection methods are used in vertical transistor designs, then manufacturing is simpler, but capacitance is higher and interconnect flexibility is reduced
Solution Approach 1:
The invention inverts the conventional interconnection approach by providing backside contacts that connect to the source and drain regions from the substrate side rather than from the top. This inversion reduces the capacitance between interconnects and active regions, improves interconnect flexibility, and enables more efficient logic device configurations
3Ease of manufacture
If finFET structures are used, then manufacturing is well-established, but capacitance is higher compared to nanosheet structures
Solution Approach 1:
The invention changes the structural parameters from fin-shaped conducting channels to thin nanosheet structures. The nanosheets have smaller thickness dimensions and different geometric characteristics that reduce the capacitance between conducting channels and surrounding structures, improving device performance while maintaining compatibility with existing manufacturing processes
Data Source
AI summary
A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.