Vertical Nanosheet Semiconductor Arrangement Reducing Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating high-density, high-performance devices due to design and fabrication issues, particularly in achieving efficient three-dimensional designs such as vertical transistors.
Innovation Solution
A semiconductor arrangement featuring a vertical unit cell architecture with nanosheets and backside interconnections, allowing for flexible interconnection of unit cells and reducing capacitance compared to finFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical transistor design is implemented to increase device density, then device density is improved, but fabrication complexity increases
Solution Approach 1:
The vertical transistor structure is segmented into distinct functional regions including source region, drain region, channel region, and gate regions positioned at different vertical levels. This segmentation allows each region to be optimized independently for its specific function while simplifying the overall fabrication process by enabling region-specific processing steps.
Solution Approach 2:
The patent transitions from planar two-dimensional transistor designs to three-dimensional vertical transistor structures. This dimensional change increases device density by utilizing the vertical dimension for stacking multiple functional regions, thereby achieving higher device density without proportionally increasing fabrication complexity through established semiconductor manufacturing processes.
2Reliability
If three-dimensional vertical designs are adopted to achieve higher performance, then device performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The vertical transistor design employs universal processing techniques and material systems that are compatible with existing semiconductor manufacturing infrastructure. The structure integrates multiple functions including charge transport, electrical isolation, and mechanical support within a unified vertical architecture, enabling higher device performance while leveraging established manufacturing capabilities.
Solution Approach 2:
The patent optimizes various physical parameters including doping concentrations, layer thicknesses, and material compositions to enhance device performance. By carefully controlling these parameters during fabrication, the design achieves superior electrical characteristics and reliability while maintaining compatibility with standard manufacturing processes.
3Quantity of substance
If finFET structure is used to increase device density, then device density is improved, but capacitance increases
Solution Approach 1:
The patent inverts the conventional finFET architecture by positioning the gate regions vertically around the channel rather than horizontally above it. This inverted vertical gate-all-around structure reduces capacitance by minimizing the overlap area between gates and source/drain regions while maintaining effective gate control, thereby achieving lower capacitance alongside high device density.
Solution Approach 2:
The vertical transistor employs thin film structures for gate electrodes and isolation layers that provide effective electrical control with minimal capacitance. The thin film gates wrap around the channel in a gate-all-around configuration, delivering strong electrostatic control while reducing parasitic capacitance compared to traditional finFET designs.
Data Source
AI summary
A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.