Self-Aligned Vertical Nanosheet Transistor Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fabricating vertical field effect transistors with consistent gate length and spacer thickness is challenging due to variations in existing deposition, masking, and etching processes, which affects device performance and density.
Innovation Solution
A self-aligned method involving reactive ion etching to create a vertical trench, filling it with a semiconductor nanosheet using an epitaxial process, and replacing a sacrificial layer with a gate stack, along with doping layers to form PN junctions, ensuring precise control over gate length and spacer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition, masking, and etching processes are used to fabricate vertical field effect transistors, then the manufacturing process can be completed, but the gate length and spacer thickness exhibit considerable variation affecting device performance
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element that defines the gate length during fabrication. This sacrificial layer is deposited conformally and then patterned, providing a precise template for the gate structure. The gate is formed over this sacrificial layer, ensuring consistent gate length without relying on subsequent etching processes that would introduce variation.
Solution Approach 2:
The sacrificial layer is deposited and patterned before the gate formation step. This preliminary action establishes the precise gate length dimensions in advance, allowing the gate to be formed with consistent dimensions without requiring high-precision etching later in the process.
2Manufacturing precision
If conventional deposition, masking, and etching processes are used to fabricate vertical field effect transistors, then the manufacturing process can be completed, but the spacer thickness exhibits considerable variation
Solution Approach 1:
The sacrificial layer serves as a mediator that defines the spacer thickness. Conformal dielectric layers are deposited over the sacrificial layer, and the spacer thickness is determined by the thickness of these conformal deposits rather than by etch depth control, eliminating a major source of variation.
Solution Approach 2:
The process replaces mechanical/physical etching-based dimension control with deposition-based dimension control. Since deposition thickness can be controlled more precisely than etch depth, this substitution improves the precision of spacer thickness control.
3Shape
If vertical trench etching is performed to create the channel structure, then the vertical channel can be formed, but the gate length control becomes difficult due to process variations
Solution Approach 1:
The sacrificial layer is patterned with the desired gate length dimensions before the vertical trench etching step. This preliminary patterning establishes the gate length template, allowing the subsequent trench etching to proceed without compromising gate length precision.
Solution Approach 2:
The sacrificial layer acts as a mediator between the trench etching process and the final gate structure. It provides a physical template that guides the formation of the gate, ensuring that the gate length is determined by the sacrificial layer dimensions rather than by the trench etching process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise control over device parameters, reducing gate-induced drain leakage and increasing effective channel length, thereby improving transistor performance and density.
Implementation Method 1
A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching
Implementation Method 2
filled, using an epitaxial process, with a vertical semiconductor nanosheet
Implementation Method 3
Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopants for a diffusion process that forms two PN junctions
Implementation Method 4
act as dopants for a diffusion process that forms two PN junctions (i.e. two doped regions on each end of a channel) in the vertical semiconductor nanosheet
Data Source
AI summary
A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.