Vertical Nanosheet CMOS Work Function Metal Separation Without Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nanosheet CMOS structures face challenges in forming p-type and n-type work function metals in vertically stacked transistors due to the complex structure, requiring additional masks and increasing device footprint.
Innovation Solution
A mask-free process is employed to form vertically stacked n-type and p-type nanosheet transistors by varying the thickness of sacrificial layers and using epitaxial growth to deposit different work function metals in nFET and pFET regions, ensuring precise metal deposition without additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional nanosheet CMOS structures are used with vertically stacked transistors, then device isolation is achieved, but additional masks are required and device footprint increases
Solution Approach 1:
The patent applies preliminary action by forming disposable gate structures and sacrificial layers in advance before the actual work function metal deposition. The sacrificial layers are positioned at different heights in the stacked structure, enabling subsequent selective removal to expose different regions for n-type and p-type work function metal formation without requiring additional masks during the metal deposition process itself.
Solution Approach 2:
The patent uses disposable gate structures and sacrificial layers as intermediary elements that facilitate the formation of different work function metals. These intermediaries are temporarily present during fabrication to enable selective metal deposition, then removed after serving their purpose, thus avoiding the need for complex mask patterns during the critical metal formation step.
2Productivity
If vertically stacked nanosheet transistors are formed, then transistor density increases, but device footprint increases due to complex structure
Solution Approach 1:
The patent transitions from planar device layout to vertically stacked three-dimensional architecture. By stacking multiple nanosheet transistors vertically, the invention achieves higher transistor density within the same footprint by utilizing the vertical dimension, thereby improving productivity without proportionally increasing the device footprint.
Solution Approach 2:
The patent implements a nested structure where multiple nanosheet transistors are stacked vertically within a compact footprint. The disposable gate structures and sacrificial layers are also nested within the stack, with each layer serving a specific function. This nested arrangement maximizes transistor density while maintaining a compact overall device footprint.
3Ease of manufacture
If mask-free process is used for work function metal deposition, then manufacturing complexity is reduced, but precision in metal deposition must be maintained
Solution Approach 1:
The patent replaces the mechanical mask system with a self-aligned chemical etching process. Instead of using physical masks to define regions for metal deposition, the invention uses the disposable gate structures and sacrificial layers as etch masks that are selectively removed through chemical processes. This substitution maintains precision through self-alignment while simplifying the manufacturing process by eliminating mask fabrication and alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves transistor density and device isolation, reducing the device footprint and enabling efficient formation of work function metals in vertically stacked transistors.
Implementation Method 1
A first set of alternating sacrificial and nanosheet layers is epitaxially grown. A second nanosheet stack comprising a second set of alternating sacrificial and nanosheet layers is epitaxially grown.
Data Source
AI summary
A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.