Vertical Nanotube Semiconductor Device for High Density Integration
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Solution Overview
Problem
Conventional nanotube semiconductor devices face electrical connection cutoff due to grain boundary defects when the bit line width is reduced, limiting their performance and integration density.
Innovation Solution
The integration of nanotube elements into integrated circuit devices, including a substrate with an electrically conductive nanotube bit line coupled to a field effect transistor, using materials like C, ZnO, and doping with elements such as Mg, Zn, and Ti, along with barrier layers to enhance adhesion and electrical connections, and a vertical nanotube structure with a nanotube pole and gate electrode to control carrier migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bit line width is reduced to increase integration density, then the integration density is improved, but grain boundary defects cut off electrical connection
Solution Approach 1:
The patent introduces a nanotube bit line as an intermediary conductive material between traditional bit lines and transistor gates. This nanotube intermediary maintains electrical connectivity at reduced dimensions where traditional materials fail due to grain boundary defects, thus resolving the contradiction between increased integration density and maintained electrical connection reliability
Solution Approach 2:
The patent changes the material parameter from traditional polycrystalline conductive materials to nanotube materials with different structural properties. This parameter change enables the bit line to function reliably at narrower widths (improved integration density) by eliminating grain boundary defects that plague conventional materials at similar dimensions
2Reliability
If conventional materials are used to maintain electrical connection, then the electrical connection is maintained, but the integration density is limited
Solution Approach 1:
The patent employs composite material structures combining nanotube channels with conventional gate materials and dielectric layers. This composite approach leverages the superior electrical properties of nanotubes for high-density integration while maintaining compatibility with existing manufacturing processes and electrical connection requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents electrical connection cutoff and improves integration density by maintaining efficient carrier migration and electrical connectivity, even at nanometer dimensions, thereby enhancing the performance and density of semiconductor devices.
Implementation Method 1
a gate electrode surrounding the nanotube channel region to control formation of the channel and carrier migration
Implementation Method 2
Carriers are migrated by ballistic transport within a nanotube having a generally uniform resistance along its length
Data Source
AI summary
A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.