Vertical Nanowire Annealing for Shape Control
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Solution Overview
Problem
Conventional methods for forming vertical nanowire structures result in bending profiles and increased line edge roughness, limiting the formation of circular or elliptical nanowires, especially during the annealing process.
Innovation Solution
A method involving the formation of semiconductor pillars using intersecting trenches filled with material, followed by a rounding process that includes annealing at higher temperatures to reduce bending profiles and enhance the shape of nanowires to circular or elliptical profiles, with a planarization process to maintain surface flushness and utilize specific mask layers like silicon nitride or oxynitride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional annealing process is used, then line edge roughness is reduced, but bending profile is formed in vertical nanowire structures
Solution Approach 1:
The patent changes the annealing temperature parameter to a higher range (900-1100°C) and extends the annealing time (30-120 minutes) to achieve both reduced line edge roughness and prevention of bending profiles. This parameter optimization allows the nanowire structures to anneal properly without deforming.
Solution Approach 2:
The patent introduces a sacrificial layer (silicon oxide or silicon nitride) as an intermediary that supports the nanowire structures during the annealing process. This intermediary layer prevents the nanowires from bending while allowing the annealing to proceed, and is subsequently removed to release the final nanowire structures.
2Shape
If higher annealing temperature and longer time are used, then rounded circular or elliptical nanowire profiles are formed, but process complexity increases
Solution Approach 1:
The sacrificial layer simplifies the overall process by enabling the use of higher annealing temperatures and longer durations to achieve rounded profiles, without requiring complex in-situ shape control mechanisms during annealing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively forms vertical nanowires with reduced line edge roughness and allows for more rounded profiles, enabling higher temperature and longer annealing times to produce circular or elliptical shapes without bending, improving the semiconductor device structure.
Implementation Method 1
the annealing process can be performed at a higher temperature and/or for a longer period of time to allow more rounded profiles to form circular or elliptical nanowires
Data Source
AI summary
A semiconductor device includes a plurality of substantially vertical semiconductor pillars on a substrate, and a hard mask layer overlying the plurality of semiconductor pillars. A contiguous portion of the hard mask layer connects two or more of the plurality of semiconductor pillars.