Vertical Nanowire Transistor Layout With Backside Power Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving higher device density and performance while minimizing substrate area and reducing parasitic capacitance in three-dimensional transistor designs, particularly in gate-all-around (GAA) transistors.
Innovation Solution
A vertical nanowire transistor with a back side power structure is introduced, where signal current flows through vertically stacked nanowires, and power supply is provided through metal lines at the back side via vias, reducing parasitic capacitance and optimizing the width-to-height ratio of unit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor designs are used, then fabrication processes are simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor designs to vertical (3D) nanowire transistor structures. The nanowire channel extends vertically through multiple metal layers, enabling the transistor to utilize the third dimension for current flow. This dimensional change increases device density by stacking multiple nanowires vertically while maintaining electrostatic control through gate structures that surround the nanowire channel in all directions.
2Area of stationary object
If substrate area is reduced for higher density, then device integration increases, but parasitic capacitance management becomes more challenging
Solution Approach 1:
By transitioning to vertical nanowire transistors, the patent reduces the horizontal footprint of each transistor while maintaining functional performance. The vertical channel allows multiple nanowires to be stacked within a smaller substrate area, increasing device density. The gate-all-around structure provides superior electrostatic control that minimizes parasitic capacitance effects even in this compact vertical configuration.
Solution Approach 2:
The patent divides the channel region into multiple discrete nanowires that are vertically stacked and independently controlled by gate structures. This segmentation allows each nanowire to be optimally sized and spaced, reducing parasitic capacitance between adjacent conductive elements while maximizing the use of vertical space. The segmented structure also enables better heat dissipation and electrical isolation between neighboring transistors.
3Reliability
If vertical nanowire structures are implemented, then device performance and control are enhanced, but fabrication complexity increases
Solution Approach 1:
The patent implements vertical nanowire channels that extend through multiple metal layers, with gate structures wrapping around the nanowires from all directions (gate-all-around). This three-dimensional architecture provides superior electrostatic control over the channel, enhancing transistor performance and reducing short-channel effects. The vertical orientation allows better heat dissipation and improved carrier mobility compared to planar structures.
Data Source
AI summary
A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.