Vertical Nanowire Cellular Interface With CMOS-Compatible Silicidation
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Solution Overview
Problem
Existing methods for manufacturing nanostructures for cellular interfacing face challenges such as inhomogeneous active layer thickness, reliance on specific substrates, and compatibility issues with CMOS technology, leading to unreliable and costly manufacturing processes.
Innovation Solution
A top-down manufacturing method is employed, structuring vertical nanowires directly over a bulk substrate without an active layer, using controlled deposition of silicon and selective silicidation to ensure consistent nanowire height and thickness, allowing integration on various substrates including transparent and flexible materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar microelectrode arrays are used for long-term cellular studies, then cell compatibility is improved, but measurement precision deteriorates due to weak cell/microelectrode interaction and signal degradation
Solution Approach 1:
The invention transitions from planar 2D microelectrodes to vertical 3D nanowire structures. The nanowires extend perpendicular to the substrate surface, increasing their interaction volume with cells and improving signal capture without compromising cell compatibility. This dimensional change allows the electrodes to penetrate deeper into the cell layer while maintaining biocompatibility.
Solution Approach 2:
The nanowire structures provide locally enhanced measurement capability at the cell interface while maintaining the overall planar substrate structure for cell culture. The vertical nanowires create localized regions of high sensitivity where they contact cells, while the bulk substrate remains compatible with long-term cell cultivation.
2Ease of manufacture
If monocrystalline silicon active layer is used for nanowire and nanofet creation, then manufacturing capability is improved, but manufacturing precision deteriorates due to thickness inhomogeneity affecting yield
Solution Approach 1:
The method performs preliminary structuring of the substrate to define nanowire locations and patterns before depositing the thin active layer. By pre-defining the structural framework, the subsequent thin layer deposition becomes more controllable and uniform, avoiding the thickness variation problems associated with trying to structure a thick monocrystalline silicon layer.
Solution Approach 2:
The invention changes the active layer thickness parameter from micrometer-scale (in existing techniques) to nanometer-scale (20-200 nm). This parameter reduction, combined with the top-down approach, enables better thickness control and uniformity across the substrate, improving manufacturing precision while maintaining ease of manufacture through standard deposition techniques.
3Manufacturing precision
If top-down manufacturing method with thin active layer is used, then manufacturing precision is improved, but device complexity increases due to sequential structuring steps
Solution Approach 1:
The method merges multiple structuring operations into a unified top-down workflow. The substrate is first structured to define nanowire positions, then the thin active layer is deposited conformally over the entire structure. This merging of steps reduces overall process complexity compared to sequentially adding and structuring separate layers, as the thin layer follows the pre-defined substrate topology throughout.
4Ease of manufacture
If conventional microelectrode fabrication is used, then ease of manufacture is improved, but adaptability deteriorates due to incompatibility with various substrate types including transparent and flexible materials
Solution Approach 1:
The top-down manufacturing method with thin active layer deposition creates a universal fabrication approach that works across diverse substrate types. The conformal deposition process adapts to different substrate geometries and materials (including transparent and flexible substrates), making the method universally applicable while maintaining ease of manufacture through standard techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures stable, repeatable, and cost-effective manufacturing of nanostructures with controlled dimensions, compatible with CMOS technology, enabling reliable long-term cellular interfacing and reduced manufacturing variability.
Implementation Method 1
creating vertical nanowires over the substrate
Implementation Method 2
depositing a silicon layer
Implementation Method 3
silicidation of the access lines and of the nanowires
Data Source
AI summary
The invention relates to a method for manufacturing a platform for cellular interfacing, the platform being manufactured over a predetermined bulk substrate, the method being a top-down method.According to the invention, such a method comprises the following steps in order:creating (E10) vertical nanowires over the bulk substrate;depositing (E30) a Si layercreating (E40) the access lines for accessing the nanowires;selective silicidation (E50) of the access lines and of the nanowires;metal structuring (E60) of the access lines;depositing (E60) an insulating layer for liquid measurement;selective removal (E70) of the insulating layer on the nanoprobes.