Vertical Nanowire Channel Structure for Sub-5 Nm Electrostatic Control
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Solution Overview
Problem
Current semiconductor processes face challenges in scaling down feature sizes due to fin distortion and quantum confinement effects, limiting the reduction of channel length in finFET technologies beyond 20 nm, which degrades electrostatic control and device performance.
Innovation Solution
A semiconductor structure with a vertical nanowire channel region using a two-dimensional material coating a dummy core, supported by a nitride pillar, and separated by spacers, allowing for channel lengths of less than 5 nm, and fabricated using integrated circuit technologies like photolithography and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If channel length is reduced below 20 nm to improve scaling, then feature size scaling is achieved, but current patterning technologies cannot fabricate features smaller than 20 nm
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed first, which then define the final nanowire channel position and dimensions. This multi-step self-aligned process enables precise sub-20 nm channel length fabrication by using the previously formed structures as templates for subsequent material deposition and patterning steps.
Solution Approach 2:
The patent introduces intermediary structures such as mandrels and spacer layers that mediate between the lithography patterning step and the final nanowire channel formation. These intermediary elements serve as temporary templates that enable the transfer of patterns at dimensions smaller than what direct lithography can achieve, effectively bridging the gap between current patterning capabilities and the desired sub-20 nm features.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.