Vertical Nanowire FETs with Low Defect Density
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Solution Overview
Problem
The challenge in developing vertical nanowire semiconductor structures for field-effect transistors (FETs) lies in achieving low defect density and high crystalline quality channels, particularly with III-V materials, to enhance electrostatic control and drive current performance, while navigating lattice mismatch issues with silicon substrates.
Innovation Solution
The approach involves growing nanowires with a larger cross-section initial surface to support multiple vertical nanowires, ensuring a low defect density by relaxing lattice strain and using a silicon substrate, which allows for defect-poor III-V nanowires to be grown, maintaining CMOS compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a silicon substrate is used to grow III-V nanowires, then CMOS compatibility is achieved, but lattice mismatch generates high defect density in the channel
Solution Approach 1:
The invention segments the nanowire growth process into two distinct stages: first growing a defect-free seed nanowire on the silicon substrate, then using its tip to nucleate multiple defect-poor nanowires. This segmentation isolates the lattice mismatch problem to the seed stage, preventing defect propagation to the final channel structures.
Solution Approach 2:
The invention performs preliminary action by first growing a defect-free seed nanowire on the silicon substrate before using it to generate the final nanowire array. This preliminary seed nanowire acts as a defect-free template, ensuring that subsequent nanowires inherit low defect density while maintaining silicon substrate compatibility.
2Power
If multiple vertical nanowires are used to increase drive current, then device performance is improved, but the area required for source/drain contacts increases
Solution Approach 1:
The invention merges multiple nanowire channels into a single integrated structure that shares common source and drain contacts. By bundling multiple vertical nanowires together, the design achieves high drive current through parallel channels while minimizing contact area through shared electrodes, directly resolving the area-power tradeoff.
Solution Approach 2:
The invention implements nesting by placing multiple nanowire channels within a compact bundled structure. The nanowires are nested closely together, allowing them to share common source and drain regions, thereby increasing drive current without proportionally increasing the contact area.
3Reliability
If nanowires are grown with smaller cross section to reduce defect density, then channel quality is improved, but drive current capability is reduced
Solution Approach 1:
The invention combines multiple thin nanowire channels into a bundled structure, where each individual nanowire maintains small cross-section for high crystalline quality, while the collective bundle provides sufficient total channel area for high drive current capability.
Solution Approach 2:
The invention changes the parameter of nanowire configuration from single thick channel to multiple thin channels. This parameter change maintains low defect density in each channel while achieving high drive current through the cumulative effect of multiple parallel channels working together.
Data Source
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AI summary
A semiconductor structure (100) comprising a first surface (129) and at least one nanowire (126), the at least one nanowire (126) being perpendicular to said first surface (129), wherein the first surface (129) is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire (126) is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface (129) of from 0% to 1%.