Vertical Nanowire FET Layout for Semiconductor Precision
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Solution Overview
Problem
Semiconductor integrated circuit devices using vertical nanowire FETs face challenges in reducing fabrication variations and minimizing area, which affect the precision and performance of the devices.
Innovation Solution
The layout structure of semiconductor integrated circuit devices incorporates standard cells with a specific arrangement of power supply interconnects, p-type, and n-type transistor regions, including active and dummy VNW FETs, to enhance fabrication precision and reduce area by sharing power supply interconnects between cell rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy VNW FETs are added to uniformize the distribution of VNW FETs, then fabrication precision is improved, but device complexity increases
Solution Approach 1:
Dummy VNW FETs are strategically placed in specific regions where active VNW FETs are sparse to uniformize the overall distribution. This local addition of dummy structures addresses the non-uniformity problem without requiring complete redesign of the entire device, thereby improving fabrication precision while limiting the increase in device complexity to only the necessary dummy elements.
2Area of stationary object
If cell rows share power supply interconnects, then area is reduced, but manufacturing precision may be affected
Solution Approach 1:
Adjacent cell rows are designed to share common power supply interconnects, merging the power distribution function across multiple rows. This consolidation reduces the total interconnect count and occupies less area, while the shared interconnects are positioned and dimensioned to maintain adequate current capacity and electrical performance, thus achieving area reduction without compromising manufacturing precision.
Data Source
AI summary
A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.