Vertical Nanowire GAA Transistor for Scaling and Leakage Control
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Solution Overview
Problem
Conventional planar MOS transistors face challenges in scaling down to 65 nm and below, leading to the development of non-planar transistor technologies like FinFETs. However, these technologies aim to achieve higher performance and miniaturization, which is not fully met by existing gate-all-around field effect transistors using nanowire structures.
Innovation Solution
A semiconductor device with a nanowire structure is vertically disposed to form a gate-all-around field effect transistor. This design includes two source/drain structures and a gate structure stacked in sequence in the vertical direction, wrapping a portion of each nanowire structure, thereby forming a vertical channel transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOS transistor is used, then manufacturing is simple, but scaling down to 65 nm and below is difficult
Solution Approach 1:
The patent transitions from planar 2D channel structure to vertical 3D nanowire structure, enabling the channel to extend in the vertical dimension while the gate wraps around it. This dimensional change allows continued scaling at sub-65nm nodes by utilizing the third dimension for channel length, effectively resolving the scaling limitation of planar transistors while maintaining manufacturability through established vertical processing techniques
2Productivity
If FinFET technology is used, then miniaturization is achieved, but channel width increase without area increase is not fully met
Solution Approach 1:
The gate structure completely surrounds the nanowire channel in a nested configuration, with the gate wrapping around the channel from all sides. This nested gate-all-around structure provides maximum channel control while achieving higher effective channel width within the same footprint compared to FinFET, as the channel is controlled from all directions rather than just the top surface
3Reliability
If gate-all-around structure is used, then channel control is improved, but current leakage reduction is not sufficient
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the gate structure and the nanowire channel, providing electrical isolation and preventing direct contact that could cause leakage. This intermediate dielectric layer enables the gate to control the channel while blocking unwanted current paths, effectively reducing leakage while maintaining the superior channel control of the gate-all-around configuration
Data Source
AI summary
A semiconductor device and fabricating method thereof includes a plurality of nanowire structures, a first source/drain structure and a second source/drain structure, a gate structure, and a gate dielectric layer. The nanowire structures are extended in a vertical direction. The first source/drain structure and the second source/drain structure are stacked in the vertical direction. The gate structure is disposed between the first source/drain structure and the second source/drain structure in the vertical direction, wherein the first source/drain structure, the second source/drain structure, and the gate structure respectively wraps a portion of each of the nanowire structures. The gate dielectric layer is disposed between the gate structure and each of the nanowire structures, and between the gate structure and the first source/drain structure.