Vertical Nanowire Memory Cell Array With Metal Gate Layer
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Solution Overview
Problem
Current conventional technologies face challenges in increasing memory density due to scaling difficulties, leading to a slowdown in memory density growth that does not keep pace with Moore's law, making it complex and expensive to achieve high capacity storage in a small area.
Innovation Solution
The development of vertical memory cell structures utilizing nanowires with a high-k dielectric material, doped polysilicon, and strategically placed bitlines and wordlines, which are electrically isolated, to enhance memory density through advanced semiconductor manufacturing techniques such as photolithographic processes and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory scaling is pursued, then memory density increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar memory architecture to vertical memory architecture, growing nanowires perpendicular to the substrate surface. This dimensional change allows memory cells to stack vertically, achieving higher density without proportionally increasing manufacturing complexity, as the vertical growth process can be integrated into existing semiconductor fabrication workflows
Solution Approach 2:
The patent implements a multi-layer vertical structure where nanowires are nested within dielectric materials, which are in turn nested within larger memory cell arrays. The bitlines and wordlines are positioned at different vertical levels, creating a nested configuration that maximizes space utilization and achieves 2-3x density improvement over conventional deep trench technology
2Quantity of substance
If memory density is increased to achieve high capacity storage in small area, then storage capacity improves, but manufacturing cost and complexity increase
Solution Approach 1:
By transitioning to vertical nanowire structures, the patent achieves higher storage capacity per unit area without requiring proportional increases in manufacturing steps. The vertical growth approach leverages existing chemical vapor deposition and etching processes, avoiding the need for entirely new manufacturing equipment or techniques
Solution Approach 2:
The patent performs preliminary patterning of nanowire locations before nanowire growth, using standard photolithographic techniques. This preliminary action defines the memory cell array layout in advance, allowing subsequent vertical growth and material deposition to proceed in a systematic manner that reduces overall manufacturing complexity
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.