Vertical Nanowire Racetrack Memory Cell Design
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Solution Overview
Problem
Current racetrack memory technologies face challenges in building vertically oriented racetrack memory cells with magnetic tunnel junctions (MTJs) due to process defects and lack of practical fabrication methods, which hinder high bit density and reliable operation.
Innovation Solution
A racetrack memory cell device with a vertically oriented nanowire and an MTJ positioned axially, integrated using standard CMOS fabrication methods and techniques, allowing for high bit density and robust operation by isolating the MTJ from the nanowire while maintaining close proximity for effective readout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the MTJ is integrated in direct contact with the nanowire to enable readout, then the readout function is achieved, but process defects are introduced that lead to pinning of domain walls
Solution Approach 1:
The patent introduces an intermediary structure (separate MTJ placement with magnetic field coupling) between the readout function and the nanowire. Instead of direct contact, the MTJ is positioned separately and couples to the nanowire through magnetic field interaction, allowing readout while preventing domain wall pinning defects
Solution Approach 2:
The patent segments the readout function from the nanowire structure by placing the MTJ as a separate component. The readout operation is decoupled from the physical nanowire structure, enabling independent optimization of both the storage element and the readout mechanism without mutual interference
2Quantity of substance
If vertically oriented racetrack memory cells are built to achieve high bit density, then the bit density is improved, but fabrication challenges increase due to lack of practical methods
Solution Approach 1:
The patent transitions from planar (2D) racetrack memory configuration to vertical (3D) configuration. By orienting the nanowire perpendicular to the wafer plane and positioning the MTJ axially along the vertical nanowire, the design achieves higher bit density by utilizing the third dimension while maintaining compatibility with standard CMOS fabrication processes
3Measurement precision
If the MTJ is positioned axially with the vertical nanowire to maintain close proximity, then the readout effectiveness is improved, but the current paths may interfere with each other
Solution Approach 1:
The patent uses magnetic field coupling as an intermediary mechanism between the MTJ and nanowire. The MTJ read current flows through the MTJ structure itself, while the magnetic field from the nanowire modulates the MTJ resistance. This indirect coupling achieves effective readout without requiring the MTJ and nanowire current paths to physically intersect
Solution Approach 2:
The patent extracts the read current path from the nanowire structure by implementing it through the MTJ device. The readout function is performed by current flowing through the MTJ, which senses the nanowire state through magnetic coupling, thereby separating the read current path from the nanowire shift current path and eliminating interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high bit density and reliable operation of racetrack memory cells with reduced process defects, achieving efficient data storage and retrieval by dissociating the MTJ readout current path from the nanowire shift current path, thus improving fabrication robustness and device reliability.
Implementation Method 1
the MTJ is used to read out the device by sensing the magnetization of the nanowire as domain walls shift through the nanowire
Implementation Method 2
utilizes current-controlled motion of magnetic domain walls in a magnetic nanowire to encode information
Data Source
AI summary
A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.