Vertical Nanowire ROM Cell Stabilizing Bit Line Load Capacitance
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Solution Overview
Problem
The existing layout structure of mask ROM using vertical nanowire FETs results in variations in load capacitance among bit lines, leading to operational delays due to differing numbers of VNW FETs connected to each bit line based on programmed states.
Innovation Solution
A semiconductor integrated circuit device with a ROM cell layout where a VNW FET is placed between a bit line and a ground potential line, with its gate connected to a word line, ensuring the bottom electrode of the transistor is connected to the bit line regardless of the stored data, thereby stabilizing load capacitance across bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of VNW FETs connected to each bit line is varied according to programmed state, then data storage capability is achieved, but load capacitance variations occur among bit lines
Solution Approach 1:
A dummy VNW FET is introduced as an intermediary element connected to the bit line. This dummy transistor does not participate in data storage but provides a consistent capacitive load to the bit line, thereby compensating for the variations caused by different numbers of active VNW FETs. The dummy FET acts as a mediator that equalizes the electrical characteristics across all bit lines regardless of their programmed state.
2Productivity
If scaling down of gate length is performed, then integration degree and operating speed are improved, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from conventional planar transistors to vertical nanowire FETs, changing the dimensional orientation of the transistor structure. By growing nanowires vertically from the substrate surface and wrapping gate electrodes around them, the design achieves higher integration density in the vertical dimension while maintaining effective gate control. This three-dimensional structure allows for smaller footprint and higher packing density without the severe off-current penalties of aggressive planar scaling.
3Productivity
If scaling down of gate length is performed, then integration degree is improved, but off current increases
Solution Approach 1:
The patent transitions from conventional planar transistors to vertical nanowire FETs, changing the dimensional orientation of the transistor structure. By growing nanowires vertically from the substrate surface and wrapping gate electrodes around them, the design achieves higher integration density in the vertical dimension while maintaining effective gate control. This three-dimensional structure allows for smaller footprint and higher packing density without the severe off-current penalties of aggressive planar scaling.
Data Source
AI summary
In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.