Vertical Nanowire Semiconductor Device Using Metal-Induced Crystallization
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Solution Overview
Problem
Existing semiconductor devices, such as low temperature polycrystalline silicon thin film transistors (LTPS TFTs), face challenges in maintaining crystal grain uniformity and yield, especially in large area displays, leading to high characteristic dispersion and reduced reliability.
Innovation Solution
A method for manufacturing a vertical Si nanowire semiconductor device using metal-induced crystallization (MIC) technology, involving the formation of a seed layer, multilayer stacking, patterning, and low-temperature heat treatment to achieve crystallization, resulting in high-quality, oriented Si nanowires with a multichannel structure for improved mobility and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excimer laser annealing is used for crystallization to manufacture LTPS TFT, then high charge mobility and high reliability are achieved, but crystal grain uniformity cannot be maintained in large area displays and yield is low
Solution Approach 1:
The patent changes the crystallization method from excimer laser annealing to metal-induced crystallization (MIC) using Ni seed layers. This parameter change enables crystallization at lower temperatures (400-600°C) with better uniformity across large areas, while maintaining high charge mobility through the formation of single-crystal or highly-oriented polycrystalline silicon grains
Solution Approach 2:
The patent introduces a metal catalyst layer (Ni seed layer) as an intermediary to facilitate silicon crystallization. The Ni layer acts as a mediator that enables controlled crystal growth through diffusion and reaction with Si, producing uniform crystal grains without requiring high-energy laser annealing
2Reliability
If conventional LTPS TFT manufacturing is used, then high charge mobility is achieved, but characteristic dispersion is high and yield is low
Solution Approach 1:
The patent changes the crystallization temperature range to 400-600°C using MIC, which provides better control over crystal grain size and distribution. This temperature control parameter improvement reduces characteristic dispersion while maintaining high charge mobility through optimized crystal orientation
Solution Approach 2:
The patent performs preliminary formation of Ni seed layers and multilayer structures before final crystallization. This preliminary action ensures uniform nucleation sites are established across the substrate, leading to consistent crystal grain formation and reduced characteristic dispersion in the final device
3Reliability
If separate ion implantation and activation processes are used, then doping and activation are achieved, but process complexity increases
Solution Approach 1:
The patent merges the doping and activation processes into a single low-temperature heat treatment step performed during MIC. The Ni catalyst layer serves dual purposes: inducing crystallization and simultaneously activating dopants, eliminating the need for separate ion implantation and activation processes
Solution Approach 2:
The Ni seed layer performs multiple functions: it acts as a catalyst for silicon crystallization, a source of Ni atoms for forming NiSi2 contact layers, and a medium for simultaneous dopant activation. This multi-functionality reduces overall process complexity while maintaining doping effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-yield semiconductor devices with high mobility and reliability, reducing product-to-product characteristic dispersion and allowing for high-performance applications like large area displays without the need for separate ion implantation or activation processes.
Implementation Method 1
performing metal induced crystallization (MIC) through low temperature heat treatment and producing reactant of the seed layer for crystallization, activation, and formation of a contact layer
Implementation Method 2
Crystal growth started in the first conductive layer in contact with the seed layer reaches the second conductive layer in the crystallization
Data Source
AI summary
A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.