Vertical Nanowire Transistors for Short-Channel Effect Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor feature sizes shrink below 50 nm, traditional planar devices face severe short-channel effects and poor sub-threshold characteristics, necessitating novel device geometries for enhanced performance and higher packing densities.
Innovation Solution
The fabrication of nanowire transistors with vertical orientations and shallow-trench-isolation (STI) structures, using CMOS-compatible processes, to form nanowire arrays with salicided source/drain contact regions and scaled high-k dielectric materials, which reduce short-channel effects and device variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar devices are used, then manufacturing process is simple, but short-channel effects and sub-threshold characteristics become severe
Solution Approach 1:
The patent transitions from traditional planar (2D) device geometry to vertical three-dimensional nanowire structures. The nanowire extends vertically from the substrate, with the channel region oriented perpendicular to the substrate surface, enabling all-around gate control and improving device performance while maintaining compatibility with existing manufacturing processes
2Productivity
If feature sizes are reduced below 50 nm, then packing density increases, but short-channel effects and device variability worsen
Solution Approach 1:
By transitioning to vertical nanowire structures, the patent achieves effective channel length control in the vertical dimension while maintaining small lateral footprints. This enables higher packing density on the substrate surface while the vertical channel provides sufficient control to mitigate short-channel effects at small feature sizes
Solution Approach 2:
The gate structure completely surrounds the nanowire channel in a nested configuration, with the gate dielectric and gate electrode wrapping around the channel region. This all-around gate control provides superior electrostatic control and reduces device variability compared to planar structures
3Reliability
If vertical nanowire structures are fabricated, then short-channel effects are minimized, but manufacturing complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: nanowire formation, source/drain region formation with salicidation, gate dielectric deposition, and gate electrode formation. Each stage uses specialized processes optimized for that particular structure formation, making the overall complex fabrication manageable through systematic segmentation
4Manufacturing precision
If high-resolution lithography is used for nanometer-gate-length patterning, then gate length precision improves, but manufacturing cost and complexity increase
Solution Approach 1:
The gate length is defined by the vertical dimension of the nanowire channel rather than lateral lithographic patterning. This dimensional transition allows nanometer-scale gate length control through vertical etching and deposition processes, avoiding the need for high-resolution lithography while achieving precise gate length definition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes short-channel effects and device-to-device variability, enabling nanometer-gate-length patterning without high-resolution lithography, thereby improving transistor performance and packing density.
Implementation Method 1
nanowire arrays with salicided source/drain contact regions
Implementation Method 2
scaled high-k dielectric materials
Data Source
AI summary
Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.