Vertical Nanowire Transistors with Shared Contacts
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing current density due to the use of horizontal nanowires, which are not efficiently packed, leading to area penalties and isolated features, making it challenging to achieve higher performance in smaller circuit structures.
Innovation Solution
A method involving the formation of vertical silicon nanowires by etching trenches in a semiconductor device structure, growing epitaxial silicon nanowires, and using insulating spacer materials to facilitate shared contacts, allowing for tighter packing and increased current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If horizontal nanowires are used, then current density can be increased, but area required increases and nanowires are isolated
Solution Approach 1:
The patent transitions from horizontal nanowire arrangement to vertical nanowire arrangement, changing the spatial dimension of nanowire placement. This vertical configuration allows multiple nanowires to be stacked in the vertical direction rather than spread horizontally, thereby increasing current density without proportionally increasing the device footprint area.
Solution Approach 2:
The patent implements shared contacts that serve multiple vertical nanowires simultaneously. Instead of each nanowire requiring separate contacts, a single contact can electrically connect to multiple nanowires, merging the connection function and reducing the overall area required for contacts and interconnect structures.
2Quantity of substance
If horizontal nanowires are used, then current density can be increased, but nanowires are isolated features
Solution Approach 1:
The patent implements shared contacts that serve multiple vertical nanowires simultaneously. Instead of each nanowire requiring separate contacts, a single contact can electrically connect to multiple nanowires, merging the connection function and reducing the overall area required for contacts and interconnect structures.
Solution Approach 2:
The shared contacts perform multiple functions: they serve as electrical connections for multiple nanowires, act as common source or drain regions, and provide mechanical support. This multi-functionality reduces device complexity by eliminating the need for separate dedicated contacts for each nanowire.
3Area of stationary object
If vertical nanowires are formed with shared contacts, then area density increases, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into distinct etching stages: first etching trenches to a first depth to form initial structures, then etching additional trenches to a second depth for shared contacts. This segmentation of the etching process into controlled stages makes the complex fabrication more manageable and precise.
Solution Approach 2:
The patent performs preliminary etching of trenches to a first depth before growing nanowires, and subsequently etches additional trenches to the same first depth and to a second depth. This preliminary structuring creates a template that guides subsequent nanowire growth and contact formation, simplifying the overall fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher current and area density in semiconductor devices by allowing multiple nanowires to share contacts, enhancing performance without area penalties, and enabling efficient fabrication of densely packed nanowire structures.
Implementation Method 1
growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches
Data Source
AI summary
Devices and methods of fabricating vertical nanowires on semiconductor devices. A doped silicon substrate, a first insulator over the doped silicon substrate, a gate conductor over the first insulator, and a second insulator over the gate conductor. Silicon nanowires extend from the top surface of the substrate through the first insulator, the gate conductor, and the second insulator. A first contact extends from the gate conductor through the second insulator, a second contact extends from the substrate through the first insulator, the gate conductor, and the second insulator layer, and an insulating spacer material is positioned between the second contact and the gate conductor.