Vertical Nitride Flash Memory With Simultaneous Complementary Operations
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Solution Overview
Problem
Existing high-density memory technologies face challenges in achieving simultaneous programming and erasing of memory channels, inefficient electron and hole injection, and optimizing array organization for high speed and density, particularly with vertical channel memory devices.
Innovation Solution
A memory device with two independent vertical memory gates and a silicon substrate, where a trench isolation between drain regions minimizes interference, and a memory gate channel oxide with trapping and non-trapping regions allows for simultaneous electron and hole injection by creating a high electric field, enabling complementary program and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar substrate with horizontal channel is used, then the device structure is simple and easy to manufacture, but the memory density and programming efficiency are limited
Solution Approach 1:
The patent transitions from a planar horizontal channel structure to a vertical channel structure by utilizing the third dimension (depth/height). The channel extends vertically through the substrate thickness, enabling higher density memory cells while maintaining manufacturability through standard semiconductor processing techniques adapted for vertical geometry.
2Ease of manufacture
If electrons are injected by scattering into the memory gate, then the injection process is simple, but the programming efficiency is low
Solution Approach 1:
The patent introduces a slanted or curved channel geometry instead of a straight horizontal path. This curvature optimizes the electron injection trajectory, allowing electrons to be injected more efficiently into the memory gate region while maintaining a relatively simple manufacturing process.
3Device complexity
If memory gates are programmed sequentially, then the control logic is simple, but the programming speed is slow
Solution Approach 1:
The patent merges the programming operations of multiple memory gates by enabling simultaneous programming through shared control mechanisms. Multiple memory gates can be programmed in parallel using common control signals and voltage lines, significantly increasing programming speed while keeping the control logic relatively simple.
4Productivity
If memory gates are placed close together to increase density, then the memory density increases, but the interference between adjacent gates increases
Solution Approach 1:
The patent applies local quality by creating spatially varying properties in the insulation structure. Different regions have different insulation characteristics - with enhanced insulation layers positioned specifically between adjacent memory gates to prevent interference, while maintaining optimal electrical characteristics in the channel regions for high-density operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed and high-density memory operations by allowing simultaneous programming and erasing of memory channels, improving injection efficiency, and reducing interference between memory gates, thus enhancing memory array performance.
Implementation Method 1
memory gate channel oxide formed between each source region and drain region and between each memory gate and silicon substrate wherein the memory gate channel oxide comprises a first trapping region and a second non-trapping region and wherein holes and/or electrons may be stored in the first trapping region
Implementation Method 2
wherein electrons and holes generated by impact ionization are drawn to their corresponding gates according to the polarity of the gate
Data Source
AI summary
A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.