Vertical Nitride Heterojunction Structure for High-Voltage Carrier Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices based on group III nitride semiconductors face limitations due to defects in their structures, which restrict their application ranges, particularly in high energy, high voltage, or high frequency applications, and they often have low voltage withstanding and carrier mobility issues.
Innovation Solution
The semiconductor device employs a foreign substrate, such as silicon or sapphire, to form a nitride semiconductor device with a vertical heterojunction, including a channel layer and barrier layers with specific doping regions to create 2DEG or 2DHG, and a body electrode to stabilize the electric field, allowing for improved voltage withstanding and carrier mobility without the need for a native substrate, thereby enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a foreign substrate is used to manufacture nitride semiconductor devices, then manufacturing cost and availability are improved, but defects and poor interface quality are introduced
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the foreign substrate and the nitride semiconductor layer. This buffer layer mediates the interface between the two materials, reducing defects and improving interface quality while still allowing the use of foreign substrates for manufacturing
Solution Approach 2:
The patent modifies the buffer layer parameters (composition, thickness, doping concentration) to optimize the interface between foreign substrate and nitride semiconductor. By changing these parameters, the buffer layer can better accommodate lattice mismatches and reduce dislocation densities
2Ease of manufacture
If conventional horizontal heterojunction structures are used, then manufacturing is simpler, but voltage withstanding capability is limited
Solution Approach 1:
The patent transitions from a conventional horizontal heterojunction structure to a vertical heterojunction structure. This dimensional change allows the device to achieve higher voltage withstanding capability by utilizing the vertical direction for electric field distribution, while the heterojunction interface remains horizontally oriented for manufacturing compatibility
3Reliability
If doping is increased to improve conductivity, then carrier concentration increases, but mobility decreases due to ion scattering
Solution Approach 1:
The patent applies different doping strategies to different regions of the device. The barrier layer is heavily doped to provide high carrier concentration and conductivity, while the channel layer remains lightly doped or undoped to maintain high carrier mobility. This local differentiation of doping quality optimizes both conductivity and mobility in their respective regions
4Speed
If polar semiconductor interfaces are used to generate 2DEG, then high conductivity and response speed are achieved, but fixed polarized charges cause threshold voltage instability
Solution Approach 1:
The patent extracts or removes the problematic fixed polarized charges from the interface by using a carefully engineered buffer layer and heterojunction structure. This allows the beneficial 2DEG formation to be maintained while eliminating the unstable polarized charges that cause threshold voltage drift
Solution Approach 2:
The patent changes the material composition and structural parameters of the heterojunction and buffer layer to control the formation and distribution of charged layers. By adjusting these parameters, the device achieves stable threshold voltage while maintaining high-speed performance through 2DEG formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a semiconductor device with improved voltage withstanding and carrier mobility, enabling better performance in high energy and high frequency applications while avoiding defects associated with foreign substrates, and allowing the device to be in a normally off state without additional electric fields.
Implementation Method 1
a doped channel layer and doped barrier layer forming a vertical heterojunction, wherein the doped channel layer includes a first doping region and a second doping region, the first doping region has a first doping concentration, the second doping region has a second doping concentration
Implementation Method 2
Polar semiconductors have many unique properties. Particularly importantly, fixed polarized charges are present at a surface of the polar semiconductor or at an interface of two different polar semiconductors. These fixed polarized charges may attract movable electron or hole carriers and thus form two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG)
Data Source
AI summary
The present invention relates to a semiconductor device, including: a first channel layer, which includes a first channel region, a first gate doped region, and a second channel region, where the second channel region is located above the first channel region, and the first gate doped region is located between the first channel region and the second channel region; a first barrier layer, where a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode, which is located below the first gate doped region and in electric contact with the 2DEG or 2DHG in the first heterojunction; a second electrode, which is located above the first gate doped region and in electric contact with the 2DEG or 2DHG in the first heterojunction; and a third electrode, which is in electric contact, in the first gate doped region, with the 2DEG or 2DHG in the first heterojunction. The present invention further includes a manufacturing method for a semiconductor device.