Vertical Nonvolatile Memory Device Fabrication
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Solution Overview
Problem
Manufacturing nonvolatile memory devices with a vertical structure is complex, leading to decreased price competitiveness and reliability compared to traditional planar structures.
Innovation Solution
A nonvolatile memory device with a vertical semiconductor structure featuring serially connected memory cells, a buried insulation layer, and interlayer insulation layers, along with string and grounding selection transistors, is developed, utilizing electron beam annealing to crystallize the semiconductor layers and enhance manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical structure is adopted to reduce device volume, then storage capacity per unit area is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to vertical (3D) stacking, where multiple memory cells are arranged along the vertical direction above a common bit line. This dimensional change increases storage capacity per unit area while the manufacturing process maintains compatibility with existing planar fabrication techniques, thus avoiding excessive manufacturing complexity
Solution Approach 2:
The vertical structure is segmented into multiple discrete memory cells (first memory cell, second memory cell, etc.) stacked along the vertical direction. Each memory cell is formed as a separate entity with distinct tunnel insulation layers, charge storage layers, and blocking insulation layers, allowing independent formation and simplifying the overall manufacturing process
2Area of stationary object
If a vertical structure is adopted to reduce device volume, then storage capacity per unit area is improved, but reliability decreases
Solution Approach 1:
The patent incorporates a ground selection transistor connected to a common source line that serves as a reference potential (ground). This ground selection transistor acts as a cushioning element that stabilizes the potential distribution in the vertical structure, preventing potential accumulation and electrical instability that could compromise reliability in high-density vertical arrangements
Solution Approach 2:
The common source line and ground selection transistor serve as intermediary elements between the vertically stacked memory cells and the external circuit. These intermediaries provide a stable reference potential and facilitate reliable signal readout from the vertical memory cell structure, ensuring signal integrity despite the increased vertical distance
3Device complexity
If conventional manufacturing processes are used for vertical structures, then manufacturing complexity is high, but cost competitiveness decreases
Solution Approach 1:
Multiple memory cells are merged vertically above a single bit line, sharing common structural elements such as the bit line, ground selection transistor, and charge storage layer formation processes. This merging reduces the total number of separate components and fabrication steps required, lowering manufacturing complexity and cost while maintaining high storage capacity
Solution Approach 2:
The vertical structure design enables a single fabrication process to create multiple functional memory cells stacked vertically. The same sequence of deposition and etching steps forms multiple tunnel insulation layers, charge storage layers, and blocking insulation layers simultaneously, making the manufacturing process universal and efficient for producing high-capacity memory devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases the reliability and economic efficiency of nonvolatile memory devices by simplifying the manufacturing process and optimizing the vertical structure, resulting in improved performance and reduced complexity.
Implementation Method 1
The amorphous semiconductor layer may be crystallized by electron beam annealing
Data Source
AI summary
Provided are a nonvolatile memory device having a vertical folding structure and a method of manufacturing the nonvolatile memory device. A semiconductor structure includes first and second portions that are substantially vertical. A plurality of memory cells are arranged along the first and second portions of the semiconductor structure and are serially connected.