Vertical Nonvolatile Memory Device With Stacked Semiconductor Layers
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Solution Overview
Problem
As memory cell sizes decrease to achieve high integration in information communication devices, the complexity of operation circuits and wirings in memory devices degrades electrical characteristics, necessitating a high degree of integration with excellent electrical characteristics.
Innovation Solution
A nonvolatile memory device with a vertical structure is developed, featuring multiple semiconductor layers with vertical memory cell arrays, shared bit lines, and integrated row decoder and page buffer circuits, including through-hole vias and partial blocks for enhanced connectivity and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are decreased to achieve high integration, then the capacity and integration degree are improved, but the electrical characteristics are degraded due to increased complexity of operation circuits and wirings
Solution Approach 1:
The patent transitions from a planar memory structure to a three-dimensional stacked structure with multiple semiconductor layers (first, second, and third layers) arranged vertically. Memory cell arrays are formed in both first and second vertical directions, enabling high-density integration while maintaining electrical performance through the spatial separation of storage and control functions across different layers.
Solution Approach 2:
The memory device is divided into functionally independent semiconductor layers: first and second semiconductor layers contain memory cell arrays for data storage, while the third semiconductor layer contains row decoder circuits and page buffer circuits for control operations. This segmentation allows each layer to be optimized independently, reducing wiring complexity and improving electrical characteristics while achieving high integration.
2Quantity of substance
If the degree of integration is increased, then the memory capacity is improved, but the chip area is increased
Solution Approach 1:
The patent utilizes vertical stacking of multiple semiconductor layers to achieve high memory capacity within a small chip footprint. By arranging memory cell arrays and control circuits in the third direction (vertical direction), the design achieves three-dimensional integration that dramatically increases storage density without proportionally increasing the planar chip area.
Solution Approach 2:
Multiple functional components are merged into a compact stacked architecture where first and second memory cell arrays share common bit lines, and row decoder circuits and page buffer circuits are integrated in the third semiconductor layer. This merging of functions across layers achieves high capacity while minimizing the required chip area.
Data Source
AI summary
A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.