3D Vertical NOR Flash Strings for Faster Low-Disturb Readout
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Solution Overview
Problem
Conventional three-dimensional vertical NAND strings face limitations due to low read current, slow read access, and susceptibility to program-disturb and read-disturb conditions, which restrict the number of transistors that can be programmed in parallel and result in higher resistivity compared to NAND strings formed in single-crystal silicon.
Innovation Solution
The implementation of three-dimensional vertical NOR Flash memory strings with multiple horizontal control gates and shared source and drain regions, allowing parallel connection of transistors, which reduces resistance and enables faster sensing and minimizes disturbance conditions, enabling the inclusion of several hundred transistors while maintaining low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional vertical NAND strings are implemented, then high-density memory storage is achieved, but read current is low and read access is slow
Solution Approach 1:
The patent inverts the conventional NAND string architecture by switching from series-connected transistors to parallel-connected transistors. This fundamental inversion changes the current flow path, allowing read current to flow through multiple parallel channels simultaneously, thereby dramatically increasing read current and reducing read access latency while maintaining high storage density.
Solution Approach 2:
The patent segments the memory string into multiple independently controllable transistor units connected in parallel between shared source and drain regions. Each transistor can be individually activated by its control gate, enabling selective read and program operations on specific memory cells without affecting others, thus improving read speed and reducing disturb conditions.
2Quantity of substance
If series-connected transistors are used in vertical NAND strings, then high-density storage is achieved, but resistivity increases
Solution Approach 1:
The patent merges multiple transistor channels into a parallel configuration where all transistors share common source and drain regions. This merging of channels creates multiple simultaneous conduction paths, effectively reducing the overall resistance and improving electrical conductivity while maintaining the same storage capacity through the parallel architecture.
3Speed
If parallel connection of transistors is implemented, then resistance is reduced and read speed is improved, but device complexity increases
Solution Approach 1:
The patent employs shared source and drain regions that serve multiple functions: they act as common electrical connections for all parallel-connected transistors, provide reference potentials for read operations, and serve as charge storage nodes. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in device complexity despite the parallel architecture.
Data Source
AI summary
A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.