Vertical NOR Memory Stack With Graded Doping and Single-Crystal Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Vertical NOR-type memory devices face challenges in scaling down due to increased resistance from polycrystalline silicon channel materials and difficulty in independently adjusting doping levels in source/drain and channel regions, leading to poor performance and integration density.
Innovation Solution
A vertical memory device with a stack of device layers on a substrate, featuring a gate stack that includes a gate conductor layer and a memory functional layer, where the doping concentration in source/drain regions decreases towards the channel region, and an interface layer is used to form steep high source/drain doping, utilizing solid phase dopant source layers for doping through diffusion, and epitaxial growth of single crystal semiconductor material to reduce resistance and enhance control over channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polycrystalline silicon is used as channel material to enable convenient stacking of vertical devices, then device stacking and integration density are improved, but resistance increases and performance deteriorates
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to single crystal semiconductor material for the channel region, fundamentally altering the crystal structure to reduce resistance while maintaining vertical stacking capability. This parameter change resolves the contradiction by providing both low resistance and stacking compatibility.
Solution Approach 2:
The patent employs a composite structure where single crystal semiconductor material forms the channel region while polycrystalline silicon or other materials may be used in source/drain regions. This composite approach allows optimization of each region's properties, achieving low resistance in the channel while maintaining manufacturing feasibility.
2Adaptability or versatility
If doping level is adjusted independently in source/drain region and channel, then device performance control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the doping process into distinct stages: first forming the channel region with its specific doping level, then separately doping the source/drain regions to different levels. This segmentation allows independent control of doping in each region while managing manufacturing complexity through process sequencing.
Solution Approach 2:
The patent applies local quality by creating different doping concentrations in specific regions - the channel region receives one doping level while source and drain regions receive different doping levels. This local differentiation achieves precise device performance control without requiring complex simultaneous doping of all regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the suppression of increased resistance and improved performance by using single crystal material for 3D memory devices, allowing for efficient stacking and independent doping control, resulting in a NOR-type memory device with enhanced integration density and performance.
Implementation Method 1
driving the dopant from the solid phase dopant source layer into opposite ends of the device layer by annealing
Implementation Method 2
polycrystalline silicon is usually used as a channel material, resulting in a greater resistance compared with using monocrystalline silicon as the channel material
Data Source
AI summary
Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device may include: a plurality of device layers stacked on a substrate, wherein each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first and second source/drain region; and a gate stack that extends vertically with respect to the substrate to pass through each device layer. The gate stack includes a gate conductor layer and a memory functional layer between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. A doping concentration in each of the first and second source/drain regions decreases towards the channel region in the vertical direction.