Vertical NOR Memory Nanosheets for Low-Resistance 3D Scaling
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Solution Overview
Problem
Vertical NOR-type memory devices face challenges in scaling down due to increased resistance from polycrystalline silicon channel materials and difficulty in independently adjusting doping levels in source/drain and channel regions.
Innovation Solution
A vertical memory device design featuring a gate stack with semiconductor layers extending vertically, where the semiconductor layers are epitaxially grown as nanosheets to reduce resistance and allow independent doping control, enabling a three-dimensional stacking configuration with improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polycrystalline silicon is used as channel material to enable vertical device stacking, then device integration density is improved, but channel resistance increases
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to single crystal semiconductor material for the channel region. This parameter change maintains the vertical device structure for high integration density while significantly reducing channel resistance due to the superior electrical properties of single crystal materials with fewer defects and grain boundaries.
Solution Approach 2:
The patent employs a composite material structure where single crystal semiconductor material forms the channel region, while polycrystalline silicon may be used in other regions such as sources or drains. This composite approach allows optimization of each region's electrical properties while maintaining overall device functionality and high integration density.
2Length of moving object
If vertical device structure is adopted to improve scaling, then device size is reduced, but control over doping levels in source/drain and channel regions becomes more difficult
Solution Approach 1:
The patent segments the vertical channel into multiple distinct regions (first channel region, second channel region, third channel region) with different doping levels. Each region can be independently doped and controlled, allowing precise adjustment of electrical properties at different vertical positions while maintaining the compact vertical device structure.
Solution Approach 2:
The patent applies local quality by assigning different doping characteristics to different vertical regions of the channel. The first, second, and third channel regions have different doping levels tailored to their specific functional requirements, enabling optimized electrical performance in each region while maintaining overall device compactness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution suppresses resistance increases and enhances integration density by using single crystal materials, effectively controlling the short channel effect and improving device performance.
Implementation Method 1
epitaxially growing a semiconductor layer on a sidewall of each device layer exposed in the processing channel through the processing channel
Data Source
AI summary
An NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device includes: a gate stack including a gate conductor layer and a memory functional layer; and a first semiconductor layer and a second semiconductor layer that surround a periphery of the gate stack. The first and second semiconductor layers are respectively located at different heights with respect to the substrate. The memory functional layer is located between the gate conductor layer and each of the first and second semiconductor layers. Each of the first and second semiconductor layers includes a first source/drain region, a channel region, and a second source/drain region that are disposed in sequence in a vertical direction. A memory cell is defined at an intersection of the gate stack and each of the first and second semiconductor layers.