Vertical NOR Memory Cell Structure With Shielded 3D Channels
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Solution Overview
Problem
NOR-type memory devices face challenges in scaling down due to planar device limitations, increased resistance with polycrystalline silicon channel materials, and crosstalk issues in three-dimensional memory cell arrangements.
Innovation Solution
A NOR-type memory device is designed with a vertically extending gate stack and semiconductor layers, using single crystalline material for improved integration density and reduced resistance, along with a conductive shielding layer to suppress crosstalk between memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polycrystalline silicon is used as channel material to stack devices vertically, then integration density is increased, but resistance increases
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to monocrystalline silicon for the channel layer, fundamentally altering the crystal structure to reduce resistance while maintaining the vertical stacking configuration for high integration density
Solution Approach 2:
The patent uses a composite structure where monocrystalline silicon is selectively applied for the channel layer while other components may use different materials, optimizing each layer's properties for its specific function
2Productivity
If memory cells are arranged in three-dimensional manner to increase integration density, then productivity is improved, but crosstalk between memory cells increases
Solution Approach 1:
The patent introduces a conductive shielding layer as an intermediary element between vertically stacked memory cells, which acts as an electric field shield to reduce crosstalk while allowing the three-dimensional arrangement to maintain high integration density
3Ease of manufacture
If planar device structure is used, then manufacturing is easier, but scaling down becomes difficult
Solution Approach 1:
The patent transitions from a planar two-dimensional device structure to a vertical three-dimensional structure, stacking multiple memory cells vertically to achieve scaling down while maintaining manufacturing feasibility through adapted fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances performance by reducing resistance and increasing integration density while controlling the short channel effect, and effectively reduces crosstalk between memory cells.
Implementation Method 1
epitaxially growing, through the processing channel, a semiconductor layer on a sidewall of each device layer exposed in the processing channel
Data Source
AI summary
Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device may include: a first gate stack extending vertically on a substrate, and a gate conductor layer and a memory functional layer; a first semiconductor layer surrounding a periphery of the first gate stack, extending along a sidewall of the first gate stack, and a first source/drain region, a first channel region and a second source/drain region arranged vertically in sequence; a conductive shielding layer surrounding a periphery of the first channel region; and a dielectric layer between the first channel region and the conductive shielding layer. The memory functional layer is located between the first semiconductor layer and the gate conductor layer. A memory cell is defined at an intersection of the first gate stack and the first semiconductor layer.