Vertical NPN MOSFET Layout for Lower-Voltage ESD Snapback
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Solution Overview
Problem
Semiconductor devices with smaller process geometries are susceptible to degradation due to electro-static discharge (ESD) and require additional ESD protection, which increases manufacturing costs due to the need for extra masks in ESD implantation.
Innovation Solution
Incorporating a parasitic vertical NPN bipolar junction transistor (BJT) with a floating p-well region for ESD protection, which provides a lower ESD triggering voltage, allowing for early discharge of ESD current to either the reference voltage Vss or power voltage Vdd, thereby reducing the risk of device damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection devices are added to protect against electro-static discharge degradation and damage, then device reliability is improved, but manufacturing cost increases due to extra masks required for ESD implant
Solution Approach 1:
The patent merges the ESD protection function with the existing vertical NPN BJT structure by utilizing the parasitic NPN transistor formed by the collector, base, and emitter regions. The floating p-well region serves as the base, the n-type diffusion region serves as the collector, and the n-type buried layer serves as the emitter. This integration eliminates the need for separate ESD implant masks while providing effective ESD protection through the snapback mechanism of the parasitic NPN transistor.
2Speed
If smaller process geometries are used to improve device speed and reduce size, then device performance is improved, but susceptibility to ESD degradation and damage increases
Solution Approach 1:
The patent employs the self-service principle by utilizing the parasitic NPN transistor that inherently exists in the CMOS device structure. The floating p-well region, n-type diffusion region, and n-type buried layer naturally form the base, collector, and emitter of the NPN transistor. During ESD events, this parasitic transistor activates through avalanche breakdown and provides snapback protection, allowing the device to protect itself without requiring additional external protection structures or increasing device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The parasitic vertical NPN BJT effectively discharges ESD current at a lower voltage, providing early protection and reducing the likelihood of device damage while potentially lowering manufacturing costs by eliminating the need for additional masks.
Implementation Method 1
the collector-base junction of the vertical NPN BJT is configured to undergo avalanche breakdown at a lower reverse bias voltage
Data Source
AI summary
A semiconductor device that includes an n-buried layer, a p-well region over the n-buried layer, an n-channel MOSFET that includes an n-drain region, and a vertical NPN BJT having a collector that is the n-drain region and a base that is the p-well region. The p-well region is floating.