Vertical Non-Volatile Memory Air Gap Insulation
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Solution Overview
Problem
The integration of a large number of cell transistors in a vertical direction within a limited substrate area is challenging for non-volatile memory devices, as it complicates the manufacturing process and can be affected by impurities present in traditional interlayer insulation layers.
Innovation Solution
The use of air gaps instead of interlayer insulation layers between transistors and control gate patterns, which are designed to be narrower near the semiconductor pattern, reduces the device height and avoids deep etching, while also preventing impurity effects, allowing for improved transistor integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interlayer insulation layers are used between transistors and control gate patterns, then the manufacturing process becomes complicated and impurities affect device performance, but using air gaps increases device height and requires deep etching
Solution Approach 1:
The patent removes the traditional interlayer insulation layer material and replaces it with air gaps between control gate patterns. This extraction eliminates the source of impurities that affect device performance while maintaining the necessary electrical insulation through the air medium, thereby improving reliability without requiring additional insulation materials.
Solution Approach 2:
Instead of using solid insulation material to separate control gate patterns, the patent inverts the approach by using air (empty space) as the insulating medium. This inversion simplifies the structure by removing material rather than adding it, eliminating impurity sources while achieving the desired electrical isolation.
2Ease of manufacture
If air gaps are used between transistors and control gate patterns, then impurity effects are prevented and manufacturing is simplified, but device height increases and deep etching is required
Solution Approach 1:
The patent extracts the interlayer insulation layer from the device structure, replacing it with air gaps. This removal simplifies the manufacturing process by eliminating the need to deposit and pattern additional insulation materials, while the air gaps naturally form during the etching process, reducing manufacturing complexity.
3Quantity of substance
If control gate patterns are made narrower near the semiconductor pattern, then integration density is improved, but etching depth increases
Solution Approach 1:
The patent applies local quality by varying the width of control gate patterns at different locations. The control gate patterns are made narrower near the semiconductor pattern where high integration density is critical, while maintaining sufficient width in other regions. This localized adjustment optimizes space utilization without uniformly increasing etching depth across the entire device.
Solution Approach 2:
The patent addresses the width-depth tradeoff by introducing dimensional variation in the control gate patterns. Instead of uniform width, the patterns transition from narrower dimensions near the semiconductor to wider dimensions farther away, effectively using the lateral dimension to compensate for etching depth constraints and achieve high integration density.
Data Source
AI summary
A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.