Vertical Non-Volatile Memory Device with Bulb-Type Gate Dielectric
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Solution Overview
Problem
Existing non-volatile memory devices with horizontal transistor structures face challenges in miniaturization and high-capacity data processing, requiring more efficient manufacturing processes and reliability.
Innovation Solution
A non-volatile memory device with a vertical structure is developed, featuring a specific layered configuration including a gate dielectric layer with a bulb-type cross-section, tunneling, charge storage, and blocking insulating layers, along with a common source line structure, to enhance manufacturing simplicity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a horizontal transistor structure is used, then manufacturing processes are conventional and simple, but miniaturization and high-capacity data processing are limited
Solution Approach 1:
The patent transitions from a conventional horizontal transistor structure to a vertical transistor structure, changing the spatial dimension of the device architecture. This dimensional change enables higher data processing capacity by stacking multiple memory cells vertically, allowing more cells to be packed into a smaller footprint area while maintaining manufacturability through adapted fabrication processes
2Manufacturing precision
If feature size is highly miniaturized, then device density increases, but process complexity and reliability challenges increase
Solution Approach 1:
The patent employs parameter changes in the form of a bulb-type cross-section structure where the width of the gate dielectric layer varies along its length. The width is larger in the lower portion (near the first interlayer insulating layer) and smaller in the upper portion (near the second interlayer insulating layer). This parameter variation optimizes the electric field distribution and stress characteristics, enabling reliable operation at highly miniaturized feature sizes while maintaining process feasibility
3Ease of manufacture
If gate dielectric layer width is constant, then manufacturing is simple, but electric field distribution and device performance are suboptimal
Solution Approach 1:
The patent applies local quality by making the gate dielectric layer width non-uniform, with different widths at different locations along the vertical axis. The larger width in the lower portion provides better electrical characteristics and stress distribution where needed, while the smaller width in the upper portion optimizes for the specific electrical requirements of that region. This location-dependent design improves device performance without significantly complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure simplifies manufacturing processes and ensures constant reliability, enabling efficient high-capacity data processing and improved performance in memory devices.
Implementation Method 1
a separation distance between side walls of the gate dielectric layer in a region of the gate dielectric layer which contacts the first gate electrode is greater than that in a region of the gate dielectric layer which contacts one of the second gate electrodes
Implementation Method 2
a tunneling insulating layer which contacts the channel region
Implementation Method 3
a charge storage layer which contacts the tunneling insulating layer
Data Source
AI summary
A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.